FPGA - compilation failure

Hello all, I'm studying labVIEW FPGA. When I tried to run my first FPGA program, the compilation always failed. Please see attached picture for details.
PCI-7830R is installed and works properly in my PC.
The software I installed -
labVIEW 2010
FPGA module 2010
xilinx 10.1 (I did not install version 11.5 since I got information from http://digital.ni.com/public.nsf/allkb/ed6fc9cf7b983cfd86256dce0072e313?OpenDocument)
Above software are evaluation version.
Does anyone know the cause of the failure? Thanks in advance for your comments.
Attachments:
compilation error.JPG ‏108 KB

Hello Christian, thank you so much for the comments. Yes, you are right. This time I follow you suggestion to simulate the VI as below, it can work. However it still can not pass compilation. It shows the same failure as I mentioned above.
Thanks again for your help,
Cole

Similar Messages

Fpga compile failure Process "Map" failed

Hi All,
We purchased a new cRIO 9068 and I am trying to get it installed into a new project with some new cards. We also upgraded our projects to LV2013 - sp1. I have been unable to complete a compile of the FPGA bitfile. It runs for 25 or so minutes and when It goes to do the "final Device Utilization(map)" it fails. It looks like I might be missing something, I but I have installed and reinstalled LV2013 and the Xilinx versions (10.1, 13.4, and 14.4) That does not seem to fix the issue.
Any Ideas on what it is looking for might also be helpful since a search for "Map" did not help.
Thanks in advance.
Solved!
Go to Solution.

Here is the log file from the failed compile.
Attachments:
XilinxLog.txt ‏2763 KB

Grrr... Xilinx compile failures

I appreciate the effort NI has put into making FPGA programming available to the unwashed masses. When things work correctly it's slicker than a greased seal in an oil factory. When things go bad it's extremely frustrating with few clues about how to fix the problem.
I've been struggling with intermittent compile failures on a cRIO-9074. The latest problem when I added code to make the fpga LED flash while the fpga is running. That generated a compile error, so I removed that code. Now it still won't compile, even though it's the exact same code as before.
I've attached the Xilinx log file. There are several different types of errors, each of which is repeated multiple times. Links are to the Xilinx KB articles:
ERROR:coreutil - ios failure
ERROR:sim:928 - Could not open destination 'PkgBeatleTypedefs.vhd' for writing.
ERROR:ConstraintSystem:58 - Constraint <INST "*oInputFalling*" TNM =
   "CcInputFallingRegs";> [toplevel_gen.ucf(141)]: INST "*oInputFalling*" does
   not match any design objects.
ERROR:ConstraintSystem:59 - Constraint <TIMESPEC "TS_AsynchMite30"= FROM
   PADS(mIoHWord_n) TO PADS(mIoDmaReq<*>) 0 ns;> [toplevel_gen.ucf(703)]: PADS
   "mIoHWord_n" not found. Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
According to Xilinx, the first error should be ignored--the design will load and run fine. Is that possible when compiling within Labview? Is there a way to run the compiler tools directly, and would that even help? The second error requires modifying the UCF file, and the third requires various tools and options not available (afaik) to LV developers.
I've been fighting the FPGA compiler for about a month. Its unpredicability is deadly for small businesses trying to deliver something to a customer. I'm about ready to throw the whole thing in the trash and go in another direction, simply because I can more accurately estimate how long it will take me to implement on a different platform.
[Edit]
I just tried recompiling the fpga vi again. This time I receive a new error:
LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
Click the 'Details' button for additional information.
Compilation Time
Date submitted: 11/28/2012 9:28 AM
Last update: 11/28/2012 9:30 AM
Time waiting in queue: 00:05
Time compiling: 01:55
- PlanAhead: 01:50
- Core Generator: 00:00
- Synthesis - Xst: 00:01
- Translate: 00:01
Attachments:
XilinxLog.txt ‏1302 KB

I'm using a 9237 in slot 3 and setting the sample rate to 1.613 kS/sec. Slots 1 and 2 have a 9411 and 9422 that I will read using the scan engine. (Some of my RT test code uses the 9422, some doesn't. It doesn't seem to be related to this problem.)
Interestingly, I added a small bit of code again to try and get the LED to flash while the FPGA is running.
...and I got all sorts of new compile errors, such as...
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 208:
   Syntax error near "downto".
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 224:
   Syntax error near "3".
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 240:
   Syntax error near "}".
ERROR:HDLCompiler:806 -
   "C:/NIFPGA/jobs/Rtxj7d7_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" Line 244:
   Syntax error near "`".
At the very end of the log it says, "Sorry, too many errors.." I guess it just gave up. I know the feeling.
I tried deleting that code and recompiling the vi, and it still won't compile. I assume if I create another new vi via copy and paste it will work again, but something weird is going on.
Attachments:
XilinxLog - FPGA Main 2 (DMA) - Added flashing LED.txt ‏141 KB

FPGA compile crashes frequently

Hello,
I have been working on an FPGA project. I am using LabView 8.5 with the FPGA module version 8.5. My target is a PCI-5640R. I am running Windows XP.
When I compile the FPGA, I frequently get errors. I originally was using arrays and clusters in the FPGA, but I got a tip that the compiler might not work well with those; so I migrated to memory blocks, but I am still getting errors.
I will attach a file with some old compile logs with errors that I got when I was using arrays and clusters. I will also attach my current project. The FPGA has a block which performs an FFT on incoming data. I am on my fourth compile attempt now. The first one failed due to circumstances outside of LabVEIWs control, but the other two logs are in the zip with the project.
I really need to get this working soon as I have a deadline approaching quickly.
Thanks
EDIT: I don't know if this helps, but twice in the past, when I started a compile, I just got a message box which said:
xflow.exe - Entry Point Not Found
The procedure entry point ?get_vendor@PM_PIC@@QBEQADXZ could not be located in the dynamic link library libPersonalityModule.dll.
However, this does not happen anymore.
Message Edited by pd2 on 07-15-2008 09:57 PM
Attachments:
project.zip ‏924 KB
some old compile failures.zip ‏229 KB

Hi
Your project LV FPGA VI compiled for me the first time.
I’ve attached the statistics for the build report.
As for why it may not be compiling all the time, or sort of randomly, I’m wondering if it may be the timing.
Base clock: ADC_0_Port_A_Clk
Requested Rate: 25.001250MHz
Theoretical Maximum: 25.661423MHz
The theoretical maximum is just a tad bit faster than the requested rate. I’m wondering if on the other compiles, that the compiler couldn’t come up with a logic layout that met the 25 MHz.
Is there any more pipelining you can do to your processing VI to get the margin up a lot higher. I saw in your processing case that there is a long chain of logic which may be pushing the theoretical time down to close to the requested time.
The other thing to try to verify this is to change the ADC clock Requested Rate down to 12.5 MHz, and see if it compiles easier.
It also might be a good idea to place your processing logic in another SCTL, passed through another FIFO. Run this off the RTSI Clock.
Jerry
Attachments:
Build.rpt.txt ‏1 KB

Is it true that bundle by name can cause FPGA compiles to fail?

Dear forum,
I have attached a full log of my experience with this apparent bug, but I will summarize it here:
I attempted to compile a labview robotics project for cRIO 9074. The code was all on the FPGA, and I'd tested it all before attempting to compile--much of it was skeleton code proving that the self test system would turn on blinky lights on the front panel. My first attempted compile received a strange failure message in stage 3 of labview's pre-xilinx compilation interface, and the message was strange mostly because it was so intensely vague. It read "An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information: Error 1000 occurred at an unidentified location. Possible reason(s): LabVIEW: The VI is not in a state compatible with this operation."
It being Tuesday the 6th of July 2010, I was unable to reach either the support staff who were on holiday or the web service, which was down for maintenance, so I began disabling pieces of my code using my debugging conditional disable statements. Eventually I found one skeletal code module, one to interface with analog flood sensors, which did not fail to compile. I compared this with another skeletal code module which did fail to compile, and after several tests noticed that adding a bundle by name from a strict type definition (but not an un-bundle by name or a standard anonymous bundle) would cause the vi to fail the compile. With several more tests I confirmed that while the vi would fail to compile with the bbn, with a standard bundle it would compile successfully all the way to the xilinx stage (by which point I didn't care, the bug was definitively pre-xilinx.)
So tonight I will be going into my code and doing a lot of replacing bundle by name blocks with anonymous bundles, but I am still haunted by the extreme vagueness of the error, and by the fact that bundle by name is usually a solid part of the FPGA development platform. It was clearly intended to work. Why didn't it?
Gray Cortright Thomas
Franklin W. Olin College of Engineering
Engineering: Robotics
Class of 2012
Needham, MA
Gray Cortright Thomas
Franklin W. Olin College of Engineering
Engineering: Robotics
Class of 2012
Needham, MA
Attachments:
gtlog2010-07-06-18-24-00.txt ‏7 KB

So I did as Donovan suggested, and this worked for the code example which I posted. But when I started trying to put more of the bundle by names back in this solution stopped working. I then went on to solve a seemingly unrelated problem with the version that had compiled using only anonymous bundle: it had been unable to run some while loops that were in subvis. When I took the code from these subvis and put the loops on the back panel of the main vi, to my utter horror, they began to function again in the compile (running on the hardware). I was afraid that it was subvis themselves that were causing this failure to run, but was relieved when my next test proved this not to be the case: I took that loop on the front panel where it worked and used edit>create subvi to put it in a subvi. It still worked. Thus I was left to search out the difference between the subvi that successfully compiled, and the subvi which compiled but didn't run--and this was that the failed subvi was part of a library. I placed the new, working, subvi in the same library and the code once again displayed the same symptoms as when it had been tested the first time: the loop would not run even once and the flow of control would never finish with the loop--it just delayed forever. This might be a problem with the way I had used the libraries, but I think everything within them was public. My guess now it that the Libraries don't behave the same way they do on the FPGA as they do on the FPGA simulator, and this is why the vis seemed to work when I simulated them. So... I took all the vis, typedefs, and globals out of the libraries and into virtual folders of the same name and... Everything works! Even bundle by name!
The implementation of project libraries in the FPGA compiler may be suboptimal in some respects, but I probed only as deep as necessary to run my code.
And this code is in 7z format because my zip file did not meet the maximum file size requirements of the forum.
It is also very possible that I misunderstood the functioning of the libraries, and the FPGA simulator was blowing sunshine up my nose when it showed them working properly in simulation. Either way, it is probably worth looking into. This weekend I might try to find the simplest project file that shows these symptoms just to prove I'm not crazy.
Gray Cortright Thomas
Franklin W. Olin College of Engineering
Engineering: Robotics
Class of 2012
Needham, MA

Fpga compilation xilinx error 'Process "Map" failed' - 'unroutable situation'

When I try to compile a Labview fpga project on our new system, it fails with the following error summary (the full Xilinx log is attached):
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:LIT:536 - IBUF symbol "aUserGpio<1>_IBUF" (output
signal=aUserGpio<1>_IBUF) has the attribute IOBDELAY set to value NONE and it
is driving an IODELAY. If the IOBDELAY attribute is on the driving PAD, it
has precedence over the IBUF one. Either the constraint or the design need
modification to prevent an unroutable situation.
Errors found during logical drc.
Design Summary
Number of errors : 1
Number of warnings : 349
Process "Map" failed
Start Time: 10:31:49 AM
End Time: 10:55:32 AM
Total Time: 00:23:43
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview 2011 version 11.0
Labview FPGA module 11.0.0
FPGA compilation tools (Xilinx12_4)
NI FlexRIO Adapter Module Support 2.2.0
NI-RIO 4.0 (FlexRIO 2.1.0)
Xilinx DRAM compilation bug fix patch from NI article id 5E4FNCDP
Xilinx clock bug fix patch from NI article id 5GFAB7DP
replaces c:\NIFPGA\programs\Xilinx11_5\ISE\xilinx\lib\nt\libPlXil_Clocks.dll; The installed version is c:\NIFPGA\programs\Xilinx12_4-> Manually copied the dll to the installed version
The Project uses the 5761 low speed clip and a DRAM FIFO.
I tried to compile it before installing any patch, after installing the DRAM patch, and after installing both patches and always got a Xilinx error after ~10 minutes compile time. The error summary shown above and the attached Xilinx log are from compiling with both patches installed.
It compiled correctly on our older system:
Hardware:
NI PXIe-1082 Chassis
NI PXIe-8133 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview2011version10.0.0
LabviewFPGAmodule10.0.0
FPGAcompilationtools (Xilinx11_5)
NIFlexRIOAdapterModuleSupport2.1.0
NI-RIO3.5.1 (FlexRIO1.5.0)
XilinxDRAMcompilationbugfixpatchfromNIarticleid5E4FNCDP
Any help / suggestions greatly appreciated,
Fabrizio
Attachments:
XilinxLog.txt ‏1482 KB

Hi Torpedotown,
Can you tell me what version of FlexRIO Adapter Module Support you are using?
The 5761 Low Speed CLIP has a constraint that doesn't work properly with some versions of the compilation tools. In order to solve this you should be able to upgrade to our latest version of FAM support, or go change the constraint manually.
For the latest version of FAM support, go to http://ni.com/info and enter code "famsoftware"
If you've modified constraint files before and feel comfortable doing it yourself, let me know and I can provide you with the details on how to do that.
Thanks!
National Instruments
FlexRIO & R-Series Product Support Engineer

Xilinx version availability for labview fpga compile

While trying to compile a Labview vi for target NI PXI 7831R, at first I didn't have
any Xilinx compile so I asked my network guy to instal it. Now it complains
that it needs 10.1 when 11.5 is available. I asked him to install the 10.1 and
he did but it isn't available to the NI FPGA compile worker. How do I solve
this?
thanks

Hi DonQuixote,
You are correct in that the PXI 7831R requires Xilinx Compile Tools 10.1. This is because this card has a Vertex II chip. You can read more about Xilinx requirements here: http://ae.natinst.com/public.nsf/webPreview/A4B20D58C051DFB386257A56007BB0B2?OpenDocument .
Have you uninstalled version 11.5? What version of LabVIEW do you have? Are you recieving an error or some other message? If so, please post a screenshot.
Thanks!
Dayna P.

FPGA Compiler

Hi All,
Sine Generator - R Series.lvproj is one of the examples in the Example Finder. The example is developed for PXI 7831 R Series card. But it’s mentioned that the example can run on PXI 7841 Series card also. So I created new target and devices (7841) in the PXI system and moved the Items to Move to my new target, then I run the Sine Generator (FPGA).vi but not successful. The compiler is hanging in the following window for hours.(I am using LabVIEW 2010 with xilnix 11.5 FPGA compiler)
Also I am facing the same problem when compiling the attached simple FPGA VI. This VI has only Sine Wave Generator function and I/O node.
Why I couldn't compile the attached simple VI or provided example VI. Please add your inputs/comments
Thanks in advance
Attachments:
test3.vi ‏36 KB

There's a trick here for significantly speeding up the compilation process on certain CPUs: http://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Multi-core-Compiling/idc-p/2301338#M297
(It looks like your CPU is supported)
Certified LabVIEW Architect, Certified TestStand Developer
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FPGA: compilation error: size of concat operation is different than size of the target

Today I got an error, for which I couldn't find a solution.
I use the PXI-7813R FPGA, with Xilinx tools 10.1
At compilation, the error I get is:
Compilation failed due to a Xilinx error.
Details:
ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 301. Size of concat operation is different than size of the target.
ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 372. Size of concat operation is different than size of the target.
-->
Total memory usage is 185944 kilobytes
Number of errors : 2 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesis" failed
Start Time: 18:25:26
End Time: 18:28:54
Total Time: 00:03:27
What can cause a concat size difference?

This is by the way the configuration:
Project: FPGAWrapperMG100125AOD.lvproj
Target: FPGA Target (RIO0, PXI-7813R)
Build Specification: fpga_integrator_AOD_random_access
Top level VI: fpga_integrator_AOD_random_access.vi
Compiling on LabVIEW FPGA Compile Cloud Service
Compilation Tool: Xilinx 10.1
Start Time: 05.07.2011 19:06:12
Run when loaded to Fpga: FALSE
Xilinx Options
Design Strategy: Custom
Synthesis Optimization Goal: Area
Synthesis Optimization Effort: Normal
Map Overall Effort Level: Default Xilinx setting
Place and Route Overall Effort Level: High
JobId: FNW72uPWorking Directory: C:\NIFPGA\compilation\FPGAWrapperMG100_FPGATarget_fpgaintegratorAO_9D5B4237
The Xilinx log is attached.
Attachments:
XilinxLog.txt ‏80 KB

Why is the FPGA compiler server so slow?

FPGA Cloud compiler is faster because NI servers are high performance, right????
Well, my Windows 7 PC is high performance, but no luck there!
Total CPU usage is never more than 25% and total memory usage (including other applications) is less than 16%.
Why does the compile server not use all available resources? has it been restricted?
How can I leverage more power from my PC?
If NI Servers can compile code quicker, there must be plausible explanation / reason?
Please advise, how to make the compile server run faster locally?
Solved!
Go to Solution.

Try this if you haven't yet:
http://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Turbo-Boost-the-speed-of-FPGA-compiles-under-Wind...
In my experience, taking advantage of Intel's Turbo Boost (my PC has i5) reduced compile time from 85 minutes to 45.
I'm currently testing Cloud Compiler and it took 110 minutes. How can Cloud Compile Server be the slowest compile?

PC Configuration for Fast LV FPGA Compile

What's the state-of-the-art PC for fast LV FPGA compile?
My life becomes short, when I have to wait 2 hours to compile a 90% usage 5640R VI on my Dell Dimension 2.8GHz PC. I toggled the hyper-threading on and off, it does not change too much.

The Xilinx tools do not make use of multiple processors so having hyperthreading or multiprocessor systems will not help compile faster. Although it will allow you to work on other things using the available processor while the compilation of the FPGA consumes the other processor. The best thing to have for your system is a lot of RAM. According to Xilinx you should have between 1-2 GB for the FPGA device in the PCI-5640R.
Regards,
Joseph D.

Stub compile failure when entity has two 1:1 relationships

I think I've found a bug in the Sun J2EE SDK (surprised? no, but looking for workaround...)
The stub code that is generated during deployment of my .ear file creates two "__reverse_item_uid" fields for my ItemBean entity.
This started when I added a second 1:1 relationship to my ItemBean. I have a PurchaseItem-Item relationship and have now added a SalesOrderItem-Item relationship. They are both 1:1 and unidirectional. See relevent section from ejb-jar.xml
<ejb-relation>
<ejb-relationship-role>
<ejb-relationship-role-name>PurchaseItem-Item</ejb-relationship-role-name>
<multiplicity>One</multiplicity>
<relationship-role-source>
<ejb-name>PurchaseItem</ejb-name>
</relationship-role-source>
<cmr-field>
<cmr-field-name>item</cmr-field-name>
</cmr-field>
</ejb-relationship-role>
<ejb-relationship-role>
<ejb-relationship-role-name>Item-PurchaseItem</ejb-relationship-role-name>
<multiplicity>One</multiplicity>
<relationship-role-source>
<ejb-name>Item</ejb-name>
</relationship-role-source>
</ejb-relationship-role>
</ejb-relation>
<ejb-relation>
<ejb-relationship-role>
<ejb-relationship-role-name>SalesOrderItem-Item</ejb-relationship-role-name>
<multiplicity>One</multiplicity>
<relationship-role-source>
<ejb-name>SalesOrderItem</ejb-name>
</relationship-role-source>
<cmr-field>
<cmr-field-name>item</cmr-field-name>
</cmr-field>
</ejb-relationship-role>
<ejb-relationship-role>
<ejb-relationship-role-name>Item-SalesOrderItem</ejb-relationship-role-name>
<multiplicity>One</multiplicity>
<relationship-role-source>
<ejb-name>Item</ejb-name>
</relationship-role-source>
</ejb-relationship-role>
</ejb-relation>
When I add my .jar to my application using the GUI of the deploytool, set everything up (jndi, generate sql, ...) run verifier is OK, and then deploy, the deploy will fail due to stub compilation failure.
If I then open up the sun-j2ee-ri.xml that is generated and found in my c:\j2sdkee1.3.1\repository\myname\applications\myapp1234.jar notice the use of two "__reverse_item_uid" fields in the following sample:
<ejb>
<ejb-name>Item</ejb-name>
<jndi-name>Item</jndi-name>
<gen-classes />
<ejb20-cmp>
<sql-statement>
<operation>storeRow</operation>
<sql>UPDATE "ItemBeanTable" SET "__reverse_item_uid" = ? , "__reverse_item_uid" = ? , "itemType" = ? , "location" = ? , "name" = ? , "peachID" = ? , "price1" = ? , "price2" = ? , "price3" = ? , "unitmeasure" = ? , "version" = ? WHERE "uid" = ? </sql>
</sql-statement>
GRRRRR!!!!! What do I do to avoid this? Can't the Sun Ref Impl generate this and the stub code smarter so that it does something like use the <ejb-relationship-role-name> as the fieldname?
Any help would be greatly appreciated :)
-Gretel

I figured it out... here's the answer in case anyone is wondering...
Use different field names for 'item' in both PurchaseItem and SalesOrderItem. In other words, here is the correct segment of ejb-jar.xml
<ejb-relation>
<ejb-relationship-role>
<ejb-relationship-role-name>SalesOrderItem-Item</ejb-relationship-role-name>
<multiplicity>One</multiplicity>
<relationship-role-source>
<ejb-name>SalesOrderItem</ejb-name>
</relationship-role-source>
<cmr-field>
<cmr-field-name>itemHack</cmr-field-name>
</cmr-field>
</ejb-relationship-role>
<ejb-relationship-role>
<ejb-relationship-role-name>Item-SalesOrderItem</ejb-relationship-role-name>
<multiplicity>One</multiplicity>
<relationship-role-source>
<ejb-name>Item</ejb-name>
</relationship-role-source>
</ejb-relationship-role>
</ejb-relation>
Simply by changing the <cmr-field-name>itemHack</cmr-field-name> from 'item' to 'itemHack' :)
Sometimes in the land of EJB development, it's the "easy" things that can waste a lot of time.

FPGA compilation not completing.- Generating Cores

When i compile my FPGA code I get the above window and will be in the same status for more than 10 hrs and still no progress and no errors are thrown by the compiler. I have tried with different Design strategy like Balanced, minimum time etc

What version of LV? OS?
Has FPGA compilation ever worked on this computer?
For test purposes, have you tried compiling a very simple FPGA VI? Does this happen with any VI you try to compile?
Can you tell by looking at the task monitor whether the compiler is still actively doing something (consuming CPU cycles) after 10 hours?
Mike...
Certified Professional Instructor
Certified LabVIEW Architect
LabVIEW Champion
"... after all, He's not a tame lion..."
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How can I reduce FPGA compiler time

Hi,
I am trying to implement a PID control loop on the FPGA of a cRIO.
The VI which runs on the FPGA target takes very long to compile (1h+).
Does anyone have an idea while the compilation takes so long and how I might be able to inprove compilation time?
The program can be found in attachment.
Best regards,
Jasper
Attachments:
PID FPGA TEST.zip ‏160 KB

Hi Jasper,
FPGA's normally take a very long time to compile compared to software compilations. 1 hour sounds about right for a slightly above average sized project. Compile times of anywhere from 2-4 hours (and longer for larger devices!) are not unheard of.
Companies who are serious about FPGA compilation and rely on quick turnaround invest in servers which contain many computers to work on the compilation (this is also why when you compile, it asks you if you would like to compile on the "local sever" (your computer) or an external server).
NI also has a cloud compiler available that will let you compile your code on their servers, however you must pay for the time. I think they offer a free trial if you wanted to see how it works.
So if you seriously need quick turnaround, you must consider some serious hardware.
Otherwise, you will have to queue up multiple compilations and let them run overnight like the rest of us.
www.movimed.com - Custom Imaging Solutions

FPGA Compile Error due to error in mapping process

Received the following error while trying to compile a FPGA VI on a PC. (Refer to attachment for details). My PC has a fresh installation of English Windows 2000 with sp4. No other software is installed except LabVIEW 8.2 & FPGA Module 8.2 & NI-RIO.
I have checked this KB and confirmed that regional settings are English. But the error still exists. I tried compiling the same VI on my laptop with Windows 2000 sp4 and it was successful. Can someone help me? Thank you very much!
FPGA Compile Error When Compiling LabVIEW FPGA VI
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.
Design Summary
Number of errors : 17
Number of warnings : 8
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
Message Edited by maimai on 01-08-2007 01:00 AM
Attachments:
FPGA Compile Error.txt ‏8 KB

Hello,
The key will of course be to isolate differences between your machines.
I wonder if the following more specific language setting could be the lingering problem. LabVIEW is a non-unicode program, and there is a language setting in Windows (at least XP) specifically for non-unicode programs. Try the following (or it's Win2K equivalent) if you haven't already:
0. Open "Control Panel"
1. Open the "Regional and Language Options"
2. On the Advanced tab, choose English (United States) from the drop-down menu under the top section "Language for non-Unicode Programs"
- This language setting is different from the setting on the "Regional Options" tab.
Any other differences you can isolate would be potentially insightful - if you have the same software versions installed in the same order on both machines, we may be looking for something a bit subtle, such as the suspected language setting.
Best Regards,
JLS
Best,
JLS
Sixclear

FPGA - compilation failure

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