GTX's receive data is error when the fpga logic resource is 70% used

Hi
My environment is : GTX core: 2.2      ISE: 14.6      FPGA: k732t-2
My GTX ip setting: no 8b10b encoding  , no data scrambing ; line rate: 2.5G,  
I use the example design code ,just change the data transmitted and the start of the frame.
My data file is attached.
Now I have a problem: when I just used the example design , the recv data is correct.
but when I add other modules to deal with the recv data, the recv data from GTX is wrong. And the wrong data is 
AAAA  ,  it is changed to AAEA or other data pattern.
When the line rate is decreased (eg. 1.25G)  the recv data is correct though the other modules is attached.
Could anyone help me give some advise ? which causes the phenomenon?
 

I have already simulated it. The simulation is correct.
And when I download the same bit file , sometimes it worked correct , but sometimes it didn't
 

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