How do I delay 1 of many outputs exiting a case structure?
I have a system here which is sort of a finite state machine, using digital I/O, I am monitoring a series of digital inputs which in turn form a binary number which is the input to a case structure. Depending on the binary string (number) that is read by the case structure, a particular series of boolean constants (T or F) exit through the case structure which are then used as my digital outputs (in my case they are controlling a series of relays). Basically, I have a condition where I would like one of the relays to be time delayed when switching in one direction, but not in the other. The problem is that when I do delay this bit, it also delays all of the bits coming from the case structure.
i.e. all the relays are delayed. How can I delay just one of them?
Well, I can't think of a really easy way. You could generate a delayed pulse on a counter output, instead of using a digital line. Otherwise you will need to keep track of the delay time in your loop somehow. The timing is only going to be as accurate (deterministic) as your loop rate, and will be operating system dependant. You may have some jitter. Attached is an example of a software delayed boolean indicator. Download both VIs.
-Jim
Attachments:
delayed_relay.vi 30 KB
boolean_trigger.vi 14 KB
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Hi,
I am going to create a vi to generate an engine speed sensor signal (a simple square wave with specific missed pulses, in my case 58 pulses “teeth” and 2 missed pulses “missed teeth”) as an analog output but in addition give me the opportunity to control parameters for example frequency online to simulate the engine speed changes during running that vi. For this purpose I have started with “Continuous Generation.vi” which is available in NI Example Finder under the following path:
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As far as I understand it is related to the time which case structure in AO C-GEN sub-vi needs for AO reconfiguration each time after changing the engine speed (update rate). How can I get rid of this delay or gap during signal generation and generating completely continuous signal?
I have to mention that obviously I changed the frequency by changing the update rate. The other possibility is to change the number of updates in one period (refer to "generate arb frequency.vi" in NI site: http://sine.ni.com/apps/we/niepd_web_display.display_epd4?p_guid=B45EACE3E48F56A4E034080020E74861) which resulted in no delay however then I can not change the frequency continuously but step by step (for example jump from 5Khz to 2.5KHz immediately) and this can not pass to my application.
Any hint is appreciated.
regards
Attachments:
Signal_generation_NIsupport.zip 81 KBHi Roozbeh,
The following example will allow you to vary the pulse train frequency during run time.
Thanks,
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Attachments:
GenDigPulseTrain-ChangingSpecs.vi 75 KB -
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Message Edited by pauldavey on 06-07-2007 12:48 PM
Attachments:
Labelling Wire from Case Diagram.vi 10 KB
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Message Edited by TonP on 06-07-2007 08:08 AM
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Go to Solution.I now understand what you were saying about inlining a subvi. I did as you said and made a subvi with a case structure and an indicator within it. I use the New VI Object node to add that subvi to the slow-inlining parent VI. Then I tried to inline it using the invoke node, but I got error 1399, which make sense. Is this what you meant for me to do, or did I misunderstand?
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Attachments:
GraphProblem_NI forum.vi 3166 KBthe easy answer is that you should clear your waveform graph before sending new data to it...
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Get_Indices.png 24 KBPladio wrote:
I've been trying to do this for a while now.
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Pladio wrote:
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Pladio wrote:
I've attached a PNG snippet of my code.
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