How to generate 8.192MHz clock on labview FPGA 7854R series card?

Hi,
I am using NI PXI-7854R series card which has Xilinx Vertex 5 FPGA on it. I am trying to derive a clock of 8.192 MHz from the 40MHz on board clock of FPGA. But it ends up giving me only 8MHz clock. Is there any way of accessing the PLL which is on Xilinx FPGA?
Regards
Solved!
Go to Solution.

If you are familliar with VHDL you can make your own "Component Level IP" (aka CLIP) with a Xilinx PLL inside. There are topics in the help and examples showing how to define a CLIP. Here is one that shows how to instantiate a DCM (similar to a PLL) in a CLIP:
http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgahelp/fpga_clip_clock_ex_code/

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How do I file Bug Report? Labview FPGA

I'm not sure if this is a software bug or what, but I'm trying to run the Analog Input example project for Labview FPGA , in "Find Examples >> Hardware Input and Output >> R Series >> Basic IO >> Analog Input - R Series".
The thing is, it works.. mostly.. I manage to send in a sine wave, and see it. However, every now and then, when I set teh Waveform Graph X-axis to autoscale, and change the Update Mode, every time I put it into mode Scope Chart, it freezes my computer, and I have to physically power off my computer and power it back up (which i'm not happy about). I'm using the default settings for the example, my card is in RSE mode, input signal at 25 Hz, 4V p-p
I doubt anyone can guess why this is happening, but is there any way to file a bug report?
Thanks,
Hardware: Quad-core Xeon 2.33 Ghz, 8 GB RAM, PXI-7583R FPGA, PXI-1036 Chassis
Software: Labview 8.6.1, LAbview FPGA 8.6., Vista 64-bit
NI Hardware: PXI-7853R, PCI-5122, PCI-6733, PXI-1036, PCI-MIO-16E-4, PCI-6110
Computer Hardware: Xeon Quad Core - 2.33 Ghz, 8 GB RAM
Software: Labview 2009, Labview FPGA 2009, Vista 64-bit, MAX 4.6, DAQmx 9.0, NI-SCOPE 3.5

1... Adding an unrelated question to a 3-month old post is not the best way to get your questions answered.
Start your own thread next time.
2... The example works fine for me. The EQUALS function works just fine for strings. Be aware of some things, though:
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Steve Bird
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How to generate a signal like this on PCI-6202 DAQ card

I want to generate a signal like the one in the attached picture.
Which have inputs like
1. Frequency
2.Duty cycle
3. No of pulses
I have created a file which gives the signal like the other one in the end which has frequency of 200us and duty cycle of 0.5% that is 1us On and 199us signal off. Now i need to include some sort of condition that when the button is pressed then the signal of the require frequency, duty cycle and no of pulses is created as input by the user on the front panel, like the one which are first part of the signals in the picture below.
Attachments:
singal_co2_laser.png ‏12 KB
gen_digital_freq_duty_noofpuleses.vi ‏21 KB

I can direct you to this forum post as an example and see if it helps you out. It seems very similar
http://forums.ni.com/t5/Multifunction-DAQ/how-to-generate-digital-signal-from-PCI-6221-like-the-one-...
Rob W.

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

How to generate sequence of pulse trains with DAQmx?

I need to generate a sequence of pulse trains with DAQmx (the card I have is a PXI-6229 card). As an example:
- 10'000 pulses at 20kHz every 5 seconds with an initial offset of 2 seconds (let's say 10 pulse trains in total).
If I use the CreateVirtualChannel.vi in "CO pulse ticks" mode, I can only specificy offset, high ticks and low ticks, but not that the sequence of pulses should be repeated after some time.
Now I thought that I could solve this problem if it were possible to multiply two counter outputs: the first counter would generate the pulses (continuously) whereas the second one would switch between low and high on a slower timescale in order to gate the first counter, thereby providing an initial offset and the "off" phases between the pulse trains.
Is it somehow possible to multiply two outputs with DAQmx and the card I have? Or is there another solution to the problem?
Thanks a lot in advance for any hints!

Hi dlanger,
what you want to do requires a little bit more work.
First look at the example "Gen Dig Pulse Train-Continuous.vi" from the LV example finder.
This example generates a continuous* pulse train. As you see, you need a sample clock VI for setting the sample mode.
* NOTE: Generating a finite pulse train with a M-series card requires 2 counter.
With a pause trigger (DAQmx trigger property node) you can gate the output of that counter.
Now you have to generate a gate-signal with the the 2nd counter. That means, only if Ctr1-out is high Ctr0-out outputs the 20 kHz-signal.
Maybe you have to adjust the times in my example a bit.
Unfortunately there is just one "small" problem: "let's say 10 pulse trains in total"
This is not possible, because a 3rd counter would be necessary (*).
As a workaround you can modify the while-loop that both tasks are cleared after 50s. This is not brilliant, but should work fine for you.
A more sophisticated way is to perform a correlated DIO. So you can generate custom pattern for multiple outputs.
A good example can you find here:
Retrigger and Repeat Finite Digital Pulse Train in LabVIEW
http://decibel.ni.com/content/docs/DOC-8473
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Generating More Than 2 Pulse Trains Using CompactDAQ
http://decibel.ni.com/content/docs/DOC-2167
Hope this helps.
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Attachments:
Gen Gated Dig Pulse Train-Continuous.vi ‏38 KB

How to generate a programmable CLK up to 32MHz with an FPGA card like PXI-7831R?

Hello,
i need to generate a programmable Clock on the FPGA card, which can be used for up to 32MHz.
I already used single-cycled-timed loops with which iam able to generate faster clocks but they are not programmable since one Channel is only allowed to be connected to one time domain at a time.
At the moment the fastest i get is a 15MHz clock with a normal while loop, which has a timer inside to delay it for slower CLK frequencies. The timer can be disabled by a case structruce, since even if the delay is 0 ticks, the fastest CLK speed is 10 MHz.
This only works with an derived CLK of 120MHz which is the maximum iam able to achieve on my system.
In all cases i use a single inverter inside the loops which keeps on inverting its own signal.
(Labview 8.2, PXI system)
Iam open to any ideas since i have run out of them.

What resolution do you need on the clock rate that you want to generate? The example below is a single cycle timed loop set to run at 100 MHz and can generate any clock rate with a resolution of 10 ns. The fastest clock that can be generated is 2 cycles of the SCTL (50 MHz). From there you can generate a clock at 3 cycles, 4 cycles, etc.
Message Edited by Christian L on 06-27-2007 02:51 PM
Christian Loew, CLA
Principal Systems Engineer, National Instruments
Please tip your answer providers with kudos.
Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
or for use in hazardous environments. You assume all risks for use of the Code and use of the Code is subject
to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense
Attachments:
varclock.JPG ‏28 KB

How to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.

how to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.
attachment:a sine signal using dds theory. Hope to get some help. Thanks!
Attachments:
FPGA DDS SineGen IP.vi ‏42 KB

you need to increment the "accumulator increment" during the duration of the chirp. the "accumulator increment" controls the frequency of the DDS cycle. by increasing it's value, you are increasing the frequency. the math for increment values follows the same math as determining the frequency to increment value.
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Viewpoint Systems, Inc.

How to generate and print 20x20 datamatrix barcode using labview?

Along with the barcode certain datas are to be added to the right of it.

Since you started a duplicate thread - I'm going to continue in here.
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How to generate and use Matlab(R2007) .dll's in Labview

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I recommend having a wrapper created around the matlab dll that converts the datatypes for you. There is a lot of fooling around with pointers involved which is very difficult in LabVIEW. btw, this got much more complicated after Matlab 7. Essentially, you need to convert your inputs into mxArrays, and then add those mxArrays to an mxArray list that you pass by pointer into the matlab dll. You also need to create a mxArray list for the outputs from the dll which you will need to extract your data out of before converting it back into a LabVIEW supported datatype. It's a big hassle. We do this pretty often, but we have created a c library that handles all the conversions, so it is feasible for us. Unfortunately, I can't share the library, but hopefully this information will help you get where you want to be.
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How to generate .sqc file in labview

Hi All,
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When I opened the sequence file(.sqc) in notepad i can see all the test limits and configurations.But when i edited any part of the sequence file in notepad and select that sequence file Labview application is not working .
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What is a .Sqc file?
How to generate this .Sqc file?
Is it possible to edit a sequence file?

Please find the attached .sqc file .You can open it in notepad. The file extension is not .seq but it is .sqc.
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Attachments:
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How to generate a pwm whose duty cycle has to be varied depending on the frequency of the input trigger??

Sir/madam,
I am quite new to the Labview FPGA module.
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Hello Manu,
You can refer
Developing a PWM Interface using LabVIEW FPGA or PWM Output with LabVIEW FPGA
How this helps.
Best Regards,
Hardik Asawa
AE
National Instruments
Message Edited by Hardik Asawa on 05-05-2010 12:46 AM

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Hello,
I need to connect the NI USB-6211 to control a digital to analog convertor chip (AD5541). However, this chip requires three input signals :1) Clock input, 2) Logic input or a synchronization signal and 3) Signal Serial Data input (CS, SCLK, DIN).
how to output the digital clock and the synchronization signal from the NI USB-6211?

Hi SaberSaber,
You should be able to use the counters to generate a pulse train that could be used for clock and synch purposes.
Hope this helps. Let us know if you have more questions.
Dave C.
Applications Engineer
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How to generate a pulse train with different pulse width and delay?

How to generate a triggered pulse train with different pulse width. for example, after each trigger signal, let's say 2 ms, then the counter output a pulse with pulsewidth of 1 ms, and then after 3 ms delay after the first pulse, the second pulse was generated with a pulse width of 4 ms. Next cycle when the trigger signal comes, the same two pulses will be generated and so on. Is it possible to achieve this by using 6601 counter card? and if yes, how to achieve this? Thanks!

Unfortunately you can not create a hardware timed pulse train with different widths on each pulse from a counter. Whilst it can be changed on the fly using software, since you require a hardware triggered signal getting the software involved will not give a huge amount of accuracy when the pulse will actually change.
So in short you can't use your 6601 card (or a counter timer) to achieve this
There are three possible Alternative solutions
1 You could use a high speed digital IO device such as the (6533/34) to generate your variable signal which would require setting up the pulse train as a series of states based around the burst transmission mode where the clock would give you your specific timing.
2 A timed analogy output (for example on a MIO card with a clock (PCI-6220 / 62xx), i.e. Not the 6704 style static analogy output cards)
3 A high speed digital waveform card such as the (, 656x , 655x, 654x, 6534, 6533 (http://www.ni.com/modularinstruments/find_right.htm) ) this could then be scripted to work with your triggering and also there is a digital waveform editor which will enable you to set up the pattern you wish to generate (http://sine.ni.com/nips/cds/view/p/lang/en/nid/13555)
Hope that helps
Tim Matthews
NI (UK)

How do i make a clock/timer that can be reset to zero?

I need to make this clock/timer to run my control off of. To be more detailed I need to ouput a steadily increasing voltage slowly over a period of time. I have my DAQ assist set up to output a voltage to my device but i can't figure out how to make the timer/clock correctly.

It seems you simply want to update the ramp at a constant dt, why would you need to reset anything?
There are two main ways to do this:
software timed: use a loop with a given delay and write single points to the output.
hardware timed: setup timing for your task and send the entire ramp to the hardware. It will do the rest. No extra code needed.
LabVIEW Champion . Do more with less code and in less time .

How to generate very fast pulses (single puls)

Hi,
I have a problem with generating fast pulses in LabView (2009 / 9.0, Win7-64enterprise).
I try to explain my project:
I have a femtosecond laser which sends pulses with a frequency of 200kHz. It mean 100fs puls 4.9999us low...100fs pulse.....
The laser have a gate which switches the laser output on and off (optic crystal --> very fast)
My task is to make it possible to send one single pulse out of the laser. You should have some user interface with LabView and enter
the amount of pulses (one, two... or more) and a big "fire" button.So we can make tests with a fixed amount of pulses.
I am very new to LabView and really dont know how to generate very short pulses. I try with a NI-USB6008 card and was possible to do some time loops
to generate something close to 100Hz. Now I have NI PCIx-6351 card. and want to try to generate pulses of 1us. How to do??? I dont see any posibility to go below 1ms.
Later on I want to try some syncronisation with the laser. I want to catch one pulse and sync to the next pulse.
Anyone able to help me with this task ?
btw: sorry for my clamsy english...
bjoern

bjoern,
OK. A gate window should be something which can be accomplished.
The USB-6008 only uses software timing so fast pulses are not possible with that device.
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How to generate 8.192MHz clock on labview FPGA 7854R series card?

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