ILA issues with Vivado 2014.3

Question

I have been trying to run the Avnet Zedboard lab regarding the 802.11 Beacon frame receiver.
http://zedboard.org/course/integrated-software-defined-radio-zynq%C2%AE-7000-all-programmable-soc
I have gotten through all the lab work and am ready now to debug my bit stream using the ILA tool.
dbg_hub and ila are clearly visible in the synthesized and implemented design, but when I load the bitstream I get the following warning messages:
refresh_hw_device [lindex [get_hw_devices] 1]
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. You must manually launch hw_server
with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4.
To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file D:/Avnet/Zynq_SDR_2014/vivado/fmcomms2_zed_802_11_RX/fmcomms2_zed_802_11_RX.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 2 ILA core(s) and 0 VIO core(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file OR
2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.
So I ran :
get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]
1
As recommended, I reduced my JTAG clock speed to 3MHz and it did not do anything either.
I also went back to Vivado 2014.3 - same problem.
So far no luck, and I have been at this for three days now - very frustrating.
You cannot use an IDE without proper debugginh tool.
Am I the only one having these issues? I see there were similar problems with Vivado 2013.3 about a year ago.
But yet not fixed???
Arne
 

Answer 1

Hi
In 2014.3 you will get these warnings if
the clock connecetd to the debug hub is not free running clock or active
the debug hub User Scan Chain setting is 2 or 4 (It is a 1 by default)
We did realize that the resolution to this warning needs to be more explicit and have fixed it in 2014.4 as follows:
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
Thanks
Smitha