Issues with placing IBUGDS, Vivado 2014.2

Question

Hi all,
I am currently using this device xc7z045ffg676-1 and am having issues with making a HR port  LVDS_25  input pair at pins AE25 and AE26 a clock source.  
The verilog code for the instantation of  the port as a clock input is as followes
module ad_lvds_clk (
clk_in_p,
clk_in_n,
clk);
input clk_in_p;
input clk_in_n;
output clk;
// wires
wire clk_ibuf_s;
// instantiations
IBUFGDS i_rx_clk_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_ibuf_s));
BUFG i_clk_gbuf (
.I (clk_ibuf_s),
.O (clk));
However as you can see from the attached screen shot the tool appears to allocate a IBUFDS and not a IBUFGDS as requested.  Is this a bug or do IBUFGDS need tobe allocated on different pins?
 I get the message 
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets smBoard/axi_ad9467_0/inst/i_if/i_adc_clk/clk_ibuf_s] >
smBoard/axi_ad9467_0/inst/i_if/i_adc_clk/i_rx_clk_ibuf (IBUFDS.O) is locked to IOB_X0Y244
and smBoard/axi_ad9467_0/inst/i_if/i_adc_clk/i_clk_gbuf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
This 
 

Answer 1


Looks like snapshot is missing, can you try attaching it again?
Thanks,
Anusheel
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