Implementing external axi lite slave using axi slave interconnect ip

Question

I am trying to implement external axi-lite slave with microblaze as the master. The slave module is the top module of the ISE project. All the axi slave signals are brought to the top level using axi-slave interconnect ip in microblaze. I am implementing this for ML605 board. I have also written a c code for driving the AXI-lite signals( read/write) from microblaze(master) side. The elf file is added to the ISE project. I generate a combined bit file and check the functunality. BUt the issue is that the execution does not go beyond idle state where the slave waits for AXI_ARVALID signal. What may be the issue. I have attached the top level vhdl code,  c code and xps screenshot.
-- axi_slave_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all ;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axi_slave_top is
port (
RS232_Uart_1_sout : out std_logic;
RS232_Uart_1_sin : in std_logic;
RESET : in std_logic;
CLK_P : in std_logic;
CLK_N : in std_logic;
led_1 : out std_logic;
led_2 : out std_logic
end axi_slave_top;
architecture STRUCTURE of axi_slave_top is
component axi_master is
port (
RS232_Uart_1_sout : out std_logic;
RS232_Uart_1_sin : in std_logic;
RESET : in std_logic;
CLK_P : in std_logic;
CLK_N : in std_logic;
axi_ext_slave_conn_0_M_AXI_AWADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_AWVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_AWREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_WDATA_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_WSTRB_pin : out std_logic_vector(3 downto 0);
axi_ext_slave_conn_0_M_AXI_WVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_WREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_BVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_BREADY_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARADDR_pin : out std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_ARVALID_pin : out std_logic;
axi_ext_slave_conn_0_M_AXI_ARREADY_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RDATA_pin : in std_logic_vector(31 downto 0);
axi_ext_slave_conn_0_M_AXI_RRESP_pin : in std_logic_vector(1 downto 0);
axi_ext_slave_conn_0_M_AXI_RVALID_pin : in std_logic;
axi_ext_slave_conn_0_M_AXI_RREADY_pin : out std_logic;
axi_ext_slave_conn_0_ACLK_pin : out std_logic
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of axi_master : component is "user_black_box";
type state is (idle, read_transaction_in_progress , write_transaction_in_progress , write_response_in_progress , complete);
signal current_state : state;
signal S_AXI_ACLK : std_logic;
signal S_AXI_ARESETN : std_logic;
-- Write Address Channel
signal S_AXI_AWADDR : std_logic_vector(31 downto 0);
signal S_AXI_AWVALID : std_logic;
signal S_AXI_AWREADY : std_logic;
-- Write Data Channel
signal S_AXI_WDATA : std_logic_vector(31 downto 0);
signal S_AXI_WSTRB : std_logic_vector(3 downto 0);
signal S_AXI_WVALID : std_logic;
signal S_AXI_WREADY : std_logic;
-- Read Address Channel
signal S_AXI_ARADDR : std_logic_vector(31 downto 0);
signal S_AXI_ARVALID : std_logic;
signal S_AXI_ARREADY : std_logic;
-- Read Data Channel
signal S_AXI_RDATA : std_logic_vector(31 downto 0);
signal S_AXI_RRESP : std_logic_vector(1 downto 0);
signal S_AXI_RVALID : std_logic;
signal S_AXI_RREADY : std_logic;
-- Write Response Channel
signal S_AXI_BRESP : std_logic_vector(1 downto 0);
signal S_AXI_BVALID : std_logic;
signal S_AXI_BREADY : std_logic;
signal combined_S_AXI_AWVALID_S_AXI_ARVALID : std_logic_vector(1 downto 0) ;
SIGNAL register_1 : std_logic_vector( 31 downto 0) ;
begin
axi_master_i : axi_master
port map (
RS232_Uart_1_sout => RS232_Uart_1_sout,
RS232_Uart_1_sin => RS232_Uart_1_sin,
RESET => RESET,
CLK_P => CLK_P,
CLK_N => CLK_N,
axi_ext_slave_conn_0_M_AXI_AWADDR_pin => s_AXI_AWADDR,
axi_ext_slave_conn_0_M_AXI_AWVALID_pin => S_AXI_AWVALID,
axi_ext_slave_conn_0_M_AXI_AWREADY_pin => S_AXI_AWREADY,
axi_ext_slave_conn_0_M_AXI_WDATA_pin => S_AXI_WDATA,
axi_ext_slave_conn_0_M_AXI_WSTRB_pin => S_AXI_WSTRB,
axi_ext_slave_conn_0_M_AXI_WVALID_pin => S_AXI_WVALID,
axi_ext_slave_conn_0_M_AXI_WREADY_pin => S_AXI_WREADY,
axi_ext_slave_conn_0_M_AXI_BRESP_pin => S_AXI_BRESP,
axi_ext_slave_conn_0_M_AXI_BVALID_pin => S_AXI_BVALID,
axi_ext_slave_conn_0_M_AXI_BREADY_pin => S_AXI_BREADY,
axi_ext_slave_conn_0_M_AXI_ARADDR_pin => S_AXI_ARADDR,
axi_ext_slave_conn_0_M_AXI_ARVALID_pin => S_AXI_ARVALID,
axi_ext_slave_conn_0_M_AXI_ARREADY_pin => S_AXI_ARREADY,
axi_ext_slave_conn_0_M_AXI_RDATA_pin => S_AXI_RDATA,
axi_ext_slave_conn_0_M_AXI_RRESP_pin => S_AXI_RRESP,
axi_ext_slave_conn_0_M_AXI_RVALID_pin => S_AXI_RVALID,
axi_ext_slave_conn_0_M_AXI_RREADY_pin => S_AXI_RREADY,
axi_ext_slave_conn_0_ACLK_pin => S_AXI_ACLK
combined_S_AXI_AWVALID_S_AXI_ARVALID <= S_AXI_AWVALID & S_AXI_ARVALID;
state_machine_decisions : process (S_AXI_ACLK )
begin
if S_AXI_aClk'event and S_AXI_aClk = '1' then
if reset = '1' then
register_1 <= x"44556677";
led_1 <= '0' ;
led_2 <= '1' ;
current_state <= idle;
else
case current_state is
when idle =>
led_1 <= '1';
led_2 <= '0';
case comb ined_S_AXI_AWVALID_S_AXI_ARVALID is
when "01" => current_state <= read_transaction_in_progress;
when "10" => current_state <= write_transaction_in_progress;
when others => NULL;
end case ;
current_state <= idle ;
when read_transaction_in_progress =>
current_state <= read_transaction_in_progress;
led_2 <= '1' ;
S_AXI_ARREADY <= S_AXI_ARVALID;
S_AXI_RVALID <= '1';
S_AXI_RRESP <= "00";
if S_AXI_RREADY = '1' then
current_state <= complete;
end if;
case (to_integer(unsigned(S_AXI_AWADDR(31 downto 0)))) is
when 0 => S_AXI_RDATA <= register_1;
when others => S_AXI_RDATA <= (others => '0');
end case ;
when write_transaction_in_progress =>
current_state <= write_transaction_in_progress;
S_AXI_AWREADY <= S_AXI_AWVALID;
S_AXI_WREADY <= '1';
-- S_AXI_RRESP <= "00";
if S_AXI_WVALID = '1' then
current_state <= write_response_in_progress;
case (to_integer(unsigned(S_AXI_AWADDR(31 downto 0)))) is
when 0 => register_1 <= S_AXI_WDATA;
when others => null;
end case;
end if;
when write_response_in_progress =>
current_state <= write_response_in_progress;
S_AXI_BVALID <= '1';
S_AXI_BRESP <= "00";
if S_AXI_BREADY = '1' then
current_state <= complete;
end if;
when complete =>
led_2 <= '0' ;
led_1 <= '0';
case combined_S_AXI_AWVALID_S_AXI_ARVALID is
when "00" => current_state <= idle;
when others => current_state <= complete;
end case;
when others => null;
end case;
end if;
end if ;
end process;
end architecture STRUCTURE;
#include <stdio.h>
#include "xil_io.h"
#define CUSTOM_IP_BASEADDR 0x7c400000
#define REGISTER_1_OFFSET 0x00
// Function prototypes
void set_custom_ip_register(int baseaddr, int offset, int value);
int get_custom_ip_register(int baseaddr, int offset);
int main (void)
int temp3;
int temp4;
printf("Test Project\n");
printf("reading from first register...");
temp3 = get_custom_ip_register(CUSTOM_IP_BASEADDR, REGISTER_1_OFFSET);
printf("Register 1 = 0x%02X\n\r", temp3);
return 0;
void set_custom_ip_register(int baseaddr, int offset, int value)
Xil_Out32(baseaddr + offset, value);
int get_custom_ip_register(int baseaddr, int offset)
int temp = 0;
temp = Xil_In32(baseaddr + offset);
return (temp);
 

Answer 1

when idle =>
led_1 <= '1';
led_2 <= '0';
case comb ined_S_AXI_AWVALID_S_AXI_ARVALID is
when "01" => current_state <= read_transaction_in_progress;
when "10" => current_state <= write_transaction_in_progress;
when others => NULL;
end case ;
current_state <= idle ;
You assign idle to current_state after you figure out what kind of transaction is happening. This will override your previous decision.
Also it is possible (at least in axi theory) there will be simultaneous read/write so separate out handling of two AxVALID conditions.