Implementing Serial Communication in LabVIEW FPGA on the Xilinx SPARTAN-3E Board

je travaille sur la carte spartan 3E et Labview avec le module FPGA.
je veux implémenter une communication serie RS232 entre spartan 3E et PC à l'aide de deux port DB9 (DTE et DCE) sur spartan 3E de tel sorte que j'envoie un cartére sur DTE et je recoie sur l'autre port DCE.
merci pour votre support.

Hi Yassagem,
It looks like you posted something very similar on this forum. I went ahead and responded on that forum post. In the future, please make sure not to duplicate forum posts.
Best,
tannerite
Tannerite
National Instruments

Similar Messages

LabVIEW FPGA driver for Xilinx SPARTAN 3E Starter Board

i need drivers for spartan 3E .

If you are at a university that has a site license for the FPGA module, the following might be of interest to you:
Using LabVIEW FPGA with the Xilinx SPARTAN-3E XUP Starter Kit
See also this discussion.
Quote from the license agreement:
...INSTALLATION AND USE OF THE LABVIEW FPGA TARGET MODULE FOR THE XILINX SPARTAN-3E STARTER BOARD (THE “TARGET MODULE”) IS LIMITED TO ACADEMIC INSTITUTIONS THAT HAVE A VALID, CURRENT “ACADEMIC TEACHING LICENSE” FROM NATIONAL INSTRUMENTS FOR THE LABVIEW FPGA MODULE. THIS TARGET MODULE MAY ONLY BE USED FOR INSTRUCTIONAL PURPOSES, SUBJECT TO THE TERMS AND CONDITIONS OF THE NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT THAT ACCOMPANIES THE SOFTWARE...
LabVIEW Champion . Do more with less code and in less time .

Labview 2010 Student Edition, will it work with the Labview FPGA module and Xilinx Spartan 3E??

Just as the title states.
I did a search here on compatibility, but I am coming up short with not much to show for it.
I have Labview 2010 student edition, 32bit and 64 bit. I am trying to do a Senior Design project for my undergrad, and I am having some issues.
I was able to download the Support for the Xilinx Spartan 3E and Labview FPGA.
I install it, it runs through the unzipping process, installs, and then mysteriously I cannot find it. I have looked through my programs list and it is not listed. I open both editions of LabView and I find ABSOLUTELY NOTHING indicating that either one has ANYTHING to do with FPGA.
Did I install it wrong? Or is it just not supported in the studend version of Labview???
Can someone help me, please?

M Boat wrote:
What about the trial version? Any chance of it being on there?
I think everything is available for download, and without activation it will be in trial mode and you have about a month (?) before the trial expires.
A trial version of the FPGA module is available for download here. I have no idea if it would work with the student version.
I would recommend to talk to your local NI sales representative for advice. Good luck.
LabVIEW Champion . Do more with less code and in less time .

Is it Possible to interface LABVIEW FPGA Module with Xilinx Spartan 3A Starter Kit

CAn anybody suggest me >>>>>>>>>>

We currently only support the Xilinx 3E XUP 500 based board (and only for academic purposes) in terms of non-NI FPGA hardware.

LabVIEW 2010 FPGA Driver for Xilinx SPARTAN 3E Starter Board

Dear Friends,
Is there any possibility to release a LabVIEW 2010 FPGA Driver for Xilinx SPARTAN 3E Starter Board?
Regards,
wedo
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Hi Brad,
So glad to get your post here!
I’m looking forward to download the new installer.
I wonder whether the new driver will support the 10/100 Ethernet Physical Layer Interface, since the last drivers aren’t support this feature!?
Also, will be any new examples included with the new driver? For instance: an example for the StartaFlash Memory; I have done an example for this but I couldn’t get it work! I don’t know why! You may check my post and the example in the following link!
http://forums.ni.com/t5/LabVIEW/Spartan-3E-StrataFlash-Memory-wrong-reading/m-p/1030898
By the way, is there any plane to develop a driver for the Spartan-3E (1600Kgate) kit? Both kits (500KGate and 1600KGate) have the sample on-board peripherals, the only difference is in the number of Gates (FPGA chip). I think all that is needed is to add the component ID (29597843---->3E1600) and revise the xc3s1600e.bsd and 3sXXXe.nph.
Thanks in advance & kindest regards,
wedo

Problems with Serial Communication using Labview 6 and Solaris 8

I am working on a Driver for a Temperature Controller. But I am stuck at the very basics. I am using Labview 6 and the platform is Solaris 8 on a SUN Ultra 60 Workstation. I can not get the Serial communication to work. When I am running raw (uncompiled) code it works (I can read from and write to ttya and ttyb) but once compiled I get error code 37 (device not found). I have tried the following steps to fix this with no luck.
1) I made sure that the "serpdrv" file is in the same folder with the executable. I also make sure the serpdrv file is added as a support file when building the app.
2) I changed from using traditional serial VI's to labview 6's new visa functions. With these "new" VI's when
I try to initiliaze the visa device and wire a control to the "visa reference" input only 1 serial port shows up (ASRL2, missing ASRL1). I am not sure if this is part of same problem or whole new issue.
3) I reinstalled both visa and labview 6.0.2 update hoping this would help with no luck
4) I placed the following entry into the ".labviewrc" file
labview.serialdevices: "/dev/ttya:/dev/ttyb"
If anybody has had the same problem I would love to hear about it and if you have any solutions
Jamie Shea

Hi Jamie,
1. Do you have NI-VISA driver installed on the machine on which you are running this executable?? If you are trying to run the executable on the same machine on which the development program has ran fine, then you can ignore this point.
2. If you have done all the changes that are suggested by other discussions related to this topic, then try changing the Port input to Visa Serial Configure.Vi from a control to a constant and try it. In some case, I have seen this to do the trick. I think this point should solve your problem. If it does do tell me. :-))

Implementing Differential Equations using Labview fpga modules on PXI-7811R

Dear,
I am working on implementing dynamic systems modeled ordinary differential equations on PXI-7811R FPGA using labview FPGA. Is there any body who can help me how to implement differential equation on PXI devices uding Labview FPGA, please? Is there any integrator in Labview FPGA, module. I used Discrete Integerator in LAbview FPGA module in Maths palette, but i hesistated if it really works . I really appreciate your help,
Gammee

Thank you for posting on the discussion forum.
You can solve differential equations using LabVIEW FPGA but you may run into some significant difficulties in doing so. If you are not tied to using FPGA, you could try using LabVIEW real-time, which may make things much easier. But if you would like to stick with FPGA, see the link below for a list of examples that may be helpful:
http://search.ni.com/nisearch/app/main/p/bot/no/ap/tech/lang/en/pg/1/sn/ssnav:ipn/q/differential%20e...
Below is a link that you can review to better understand the functionality of the discrete integrator should you choose to go that route:
http://zone.ni.com/reference/en-XX/help/371599B-01/lvfpga/discrete_normalized_integrator/
I hope that helps.
Best,
Rachel
Rachel D.
Applications Engineer
National Instruments

Serial Communication using Labview with Tiva C launchpad ARM cortex M4

I am able to comunicate perfectly between labview and launchpad at 9600 baudrate..When i trying to communicate with bauadrate of 115200 labview gives error "specifed state of attribute is not valid"
I tried to communicate with serial monitor comes with arduino and its well work with it at 115200 baudrate...
Awaiting for your replay!!!

piZviZ wrote:
Only data rate working is 9600 between labview and launchpad(arm cortex m4).Where all data rates work between Arduino serial port monitor and launchpad(arm cortex m4).
Since the only thing that changed is the Launchpad, then that must be the issue. Are you sure this device can handle more than just the 9600 baud rate? Are you sure you are even setting the baud rate on this device?

Labview fpga vs xilinx ise

hi all
i am new to fpga and my question is fairly simple one which one is better ?
labview fpga or the xilinx ise platform ?
or does it depend upon the application?
Regards
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It always depends on the application. Better in what way?
I like programming in LabVIEW, so I think LabVIEW FPGA is a much better choice. Learn just a little more than regular LabVIEW and you can program an FPGA! Unless you have experience using ise, I suspect LabVIEW would be the easier route.
If you are looking at price, maybe ise wins. It isn't cheap to get buy LabVIEW and the FPGA module (and probably RT module) so you have all the tools.
If the task is very complex, you might manage to make the program slightly more efficient using a lower level tool like ise. You might shave off a few nanoseconds of loop time. In 99.9% of the cases, this is unlikely. LabVIEW code does a pretty good job converting over to FPGA.
Bruce
Bruce Ammons
Ammons Engineering

Communication problem between FPGA VI and Host-PC VI

Dear,
I am trying to set up communication between an FPGA an the host-PC using FPGA FIFO's.
The communication still has some problems and I don't know what would cause them.
Labview gives me the following reason "The transfer did not complete within the timeout period or within the specified number of retries."
What is wrong with my labview program? How can i solve this?
The Project can be found in attachment.
Best regards,
Jasper Beurms
Solved!
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Attachments:
CEC20_02.zip ‏150 KB

Hello Jasper,
Are you fully familiar with how DMA FIFOs work on a cRIO?
Some general questions:
- Is there a specific reason that you need to use DMA FIFOs?
You seem to only require a 10 msec acquisition rate?
- Wouldn't it be easier to just use the Scan Engine in the case you don't need to go below 10 msec?
The Scan Engine should allow you to do acquisitions at this rate without even having to implement FPGA code yourself.
Another benefit is that the Shared Variables created/published by the Scan Engine are also by default visible over the network/
If want to use DMA FIFOs, then I would suggest you take a look at the Compact RIO Developer's Guide: http://www.ni.com/compactriodevguide/
I would advise that you read out the DMA FIFOs on a VI that is running on the RT Controller (RT VI) and then send those values from the RT VI over the network to your Windows VI.
You could use for example Shared variables to sent values from the RT VI to the Windows Host VI.
Another solution might be to use network streams or more custom TCP/IP communication.
If these concepts are new to you, then please have look at the Compact RIO Developer's Guide: http://www.ni.com/compactriodevguide/
This Guide should explain you all the basics you need to know.
If something is unclear or requires further explanation, then please let me know.
Kind Regards,
Thierry C - Applications Engineering Specialist Northern European Region - National Instruments
CLD, CTA
If someone helped you, let them know. Mark as solved and/or give a kudo.

OBD1 ALDL communication with Labview VISA

Hello all,
I am new to serial communication with labview.
Task:
trying to send a command and receive data from a 1987 corvettes ECM using VISA serial block in labview.... and failing hard
Troubleshooting the problem:
Hardware: works with EFI live V4 (software that communicates with cars), send and receives data all day long, so my hardware is not the problem
software: it is something i am doing wrong in my coding
Example code form EFI live V4:
37:30.137: Send: $80,$57,$01,$00,$28
37:30.137: Finished writing frame
37:30.137: Wait 10 ms after writing, before reading...
37:30.147: Start reading frame
37:30.147: Aldl frame header byte: $80
37:30.147: Aldl frame length byte: $57
37:30.147: Recv: $80,$57,$01,$00,$28
37:30.147: Finished reading frame
37:30.147: MAX232 echo: $80,$57,$01,$00,$28
37:30.147: Wait 10 ms after writing, before reading...
37:30.157: Start reading frame
37:30.160: Aldl frame header byte: $80
37:30.160: Aldl frame length byte: $95
37:30.241: Recv: $80,$95,$01,$1E,$5B,$00,$00,$00,$00,$00,$44,$44,$1D,$00,$9C,$D6,$00,$00,$FF,$66,$00,$80,$80,$00,$80,$64,$80,$FF,$00,$80,$00,$27,$27,$00,$00,$00,$77,$00,$3A,$00,$43,$00,$00,$00,$00,$00,$00,$00,$00,$01,$BD,$00,$00,$00,$00,$00,$00,$D5,$2A,$22,$00,$07,$00,$00,$0C,$00,$DE
37:30.241: Finished reading frame
Example code protocol i tryed into the visa block in labview:
$80,$57,$01,$00,$28
$80,$57,$01,$00,$28\n
$80,$57,$01,$00,$28\r\n
$80$57$01$00$28
$80$57$01$00$28\n
$80$57$01$00$28\r\n
80 57 01 00 28
80 57 01 00 28\n
80 57 01 00 28\r\n
8057010028
8057010028\n
8057010028\r\n
VISA read Result:
i just get an eco back of the same command i sent
Question:
is there something simple i am missing in the command protocol or a possible setting i am overlooking?
also what is the purpose of the “$” in the Hex command?
background info:
vehicle : 1987 corvette
ECM type: 16198259
com. protocol : ALDL OBD1
labview v8.5
baud rate: 8192
data: 8 bit
parity: none
stop: 1
buffer size: 256

Are you actually supposed to be sending hex? You need details on the actual format of the data. I don't think viewing the output of some other program will tell you what is truly being sent and received unless its a sniffer such as portmon.
You can right click on the string control and select hex display. You also did not include the actual VI so no one knows if you have it set to send \r and \n correctly.

UART and/or serial communication

Hello, Labview Experts,
Our sensor node uses UART protocol to communicate. We are able to convert it to serial signals. Does anyone know how we can manipulate serial communication in LabVIEW?
Thanks,
ck

Use the VISA vi's. Search for serial and VISA in the labview examples.

LZW decompression in LabVIEW FPGA?

This is a long shot, but might as well ask. Has anyone implemented LZW decompression in LabVIEW FPGA, and if so, would you be willing to share your code?

I know someone has done it so it is possible, but I don't know of a public source. If you are in a time crunch to get an implementation working, you could get one of the open source VHDL, Verilog, or SystemC implementations and import that with the IP Integration Node or as a CLIP. Various discussions on the forums and the documentation describe how this can be done.

FFT on LabVIEW FPGA

Hello Everyone,
I am doing a project in which i have to done FFT on data on LabVIEW FPGA. The data is actually a pixel value of an image which are first converted to imaginary parts and then their exponential is to computed, after taking exponential their FFT is to perform. I am new to Labview FPGA but know something about LabVIEW. If any one can guide me from where to start and how to do this, it will be of great help to me. I studied a tutorial on NI website but didn't get much out of it. I have NI cRIO-9024 LabVIEW FPGA. Any help will be appreciated.
Thanks
Regards

Hello!
We don’t have any finished VI’s shipping with the LabVIEW FPGA Module that does FFT. However if you can VHDL or have access to HDL IP Cores you are able to make use of the HDL node and implement it yourself. Then tests needs be to done in order to find if the VI can execute fast enough. If you search on HDL node on our website you will find more information about how to implement code using that function. You can also provide information to our R&D that you would like to see this feature in the future here:
http://digital.ni.com/applications/psc.nsf/default?OpenForm&temp1=&node=
Regards,
Jimmie Adolph
Systems Engineer Manager, National Instruments Northern Region
Bring Me The Horizon - Sempiternal

Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?

Dear Friends,
Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers!
1-      Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money?
I’m looking for a comparison can show the following points:
·         The Code size and speed optimization.
·         Developing time.
·         Compiling time.
·         Verifying time.
·         Ability to developing in future.
·         …etc.. 2-
I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
3-      I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
4-      I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,599&Prod=XUPV5
Thnaks & regards,Walid
Solved!
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Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism. I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
Check out the FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores

Implementing Serial Communication in LabVIEW FPGA on the Xilinx SPARTAN-3E Board

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