Labview fpga vs xilinx ise

hi all
i am new to fpga and my question is fairly simple one which one is better ?
labview fpga or the xilinx ise platform ?
or does it depend upon the application?
Regards
Solved!
Go to Solution.

It always depends on the application. Better in what way?
I like programming in LabVIEW, so I think LabVIEW FPGA is a much better choice. Learn just a little more than regular LabVIEW and you can program an FPGA! Unless you have experience using ise, I suspect LabVIEW would be the easier route.
If you are looking at price, maybe ise wins. It isn't cheap to get buy LabVIEW and the FPGA module (and probably RT module) so you have all the tools.
If the task is very complex, you might manage to make the program slightly more efficient using a lower level tool like ise. You might shave off a few nanoseconds of loop time. In 99.9% of the cases, this is unlikely. LabVIEW code does a pretty good job converting over to FPGA.
Bruce
Bruce Ammons
Ammons Engineering

Similar Messages

Digital Electronics FPGA Board with Xilinx ISE

Hi,
I've a design in Xilinx ISE. I Synthesized and created the Bit map file.
How can I export this bitmap file to the NI Digital Electronics FPGA is board? I tried using Adept to program, but the tool didn't detect FPGA board.
Thanks in advance.

Hello,
The Adept Program is something that is made by Digilent. This application isn't meant for being used with non-digilent FPGAs such as the one on the NI Digital Electronics FPGA Board. The FPGA on this board is made by Xilinx so you have to use Xilinx tools in order to deply files to the FPGA (assuming you're not using LabVIEW FPGA). Specifically, you should use the Xilinx iMPACT Software, version 10.x or later, which is part of the ISE WebPACK kit. You can get this software from www.xilinx.com/ise.
If you still have questions about deploying your files to the FPGA, you can refer to the following resource.
Xilinx iMPACT Examples:
http://www.ni.com/white-paper/8671/en/
I hope this helps!
Regards,
Cameron T
Applications Engineer
National Instruments

LabVIEW FPGA driver for Xilinx SPARTAN 3E Starter Board

i need drivers for spartan 3E .

If you are at a university that has a site license for the FPGA module, the following might be of interest to you:
Using LabVIEW FPGA with the Xilinx SPARTAN-3E XUP Starter Kit
See also this discussion.
Quote from the license agreement:
...INSTALLATION AND USE OF THE LABVIEW FPGA TARGET MODULE FOR THE XILINX SPARTAN-3E STARTER BOARD (THE “TARGET MODULE”) IS LIMITED TO ACADEMIC INSTITUTIONS THAT HAVE A VALID, CURRENT “ACADEMIC TEACHING LICENSE” FROM NATIONAL INSTRUMENTS FOR THE LABVIEW FPGA MODULE. THIS TARGET MODULE MAY ONLY BE USED FOR INSTRUCTIONAL PURPOSES, SUBJECT TO THE TERMS AND CONDITIONS OF THE NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT THAT ACCOMPANIES THE SOFTWARE...
LabVIEW Champion . Do more with less code and in less time .

Labview 2010 Student Edition, will it work with the Labview FPGA module and Xilinx Spartan 3E??

Just as the title states.
I did a search here on compatibility, but I am coming up short with not much to show for it.
I have Labview 2010 student edition, 32bit and 64 bit. I am trying to do a Senior Design project for my undergrad, and I am having some issues.
I was able to download the Support for the Xilinx Spartan 3E and Labview FPGA.
I install it, it runs through the unzipping process, installs, and then mysteriously I cannot find it. I have looked through my programs list and it is not listed. I open both editions of LabView and I find ABSOLUTELY NOTHING indicating that either one has ANYTHING to do with FPGA.
Did I install it wrong? Or is it just not supported in the studend version of Labview???
Can someone help me, please?

M Boat wrote:
What about the trial version? Any chance of it being on there?
I think everything is available for download, and without activation it will be in trial mode and you have about a month (?) before the trial expires.
A trial version of the FPGA module is available for download here. I have no idea if it would work with the student version.
I would recommend to talk to your local NI sales representative for advice. Good luck.
LabVIEW Champion . Do more with less code and in less time .

NI LabVIEW 2013 FPGA Module Xilinx Tools 10.1 Download Troubles

I am trying to download the Xilinx Tools 10.1 to use with a 9113 chassis in LV2011. Based on this white paper the compiler below should work just fine. The problem is I can't get it to download all the way.
I can't seem to get past ~336MB using the standard or NI downloader. Any ideas? Anybody else having this problem?
http://www.ni.com/download/labview-fpga-module-2013/4249/en/
thanks,
-PBD
Solved!
Go to Solution.

Well... on the bright side, you don't want 10.1 anyway!
Virtex-5 LX50 <- REQUIRES Xilinx 14.4.
10.1 is only for Virtex-II devices! (...after LabVIEW 2009 that is, just so everyone reading this knows).
soo.... try this link: http://www.ni.com/download/labview-fpga-module-2013/4248/en/
Cheers!
TJ G

Fpga compilation xilinx error 'Process "Map" failed' - 'unroutable situation'

When I try to compile a Labview fpga project on our new system, it fails with the following error summary (the full Xilinx log is attached):
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:LIT:536 - IBUF symbol "aUserGpio<1>_IBUF" (output
signal=aUserGpio<1>_IBUF) has the attribute IOBDELAY set to value NONE and it
is driving an IODELAY. If the IOBDELAY attribute is on the driving PAD, it
has precedence over the IBUF one. Either the constraint or the design need
modification to prevent an unroutable situation.
Errors found during logical drc.
Design Summary
Number of errors : 1
Number of warnings : 349
Process "Map" failed
Start Time: 10:31:49 AM
End Time: 10:55:32 AM
Total Time: 00:23:43
Hardware:
NI PXIe-1071 Chassis
NI PXIe-8108 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview 2011 version 11.0
Labview FPGA module 11.0.0
FPGA compilation tools (Xilinx12_4)
NI FlexRIO Adapter Module Support 2.2.0
NI-RIO 4.0 (FlexRIO 2.1.0)
Xilinx DRAM compilation bug fix patch from NI article id 5E4FNCDP
Xilinx clock bug fix patch from NI article id 5GFAB7DP
replaces c:\NIFPGA\programs\Xilinx11_5\ISE\xilinx\lib\nt\libPlXil_Clocks.dll; The installed version is c:\NIFPGA\programs\Xilinx12_4-> Manually copied the dll to the installed version
The Project uses the 5761 low speed clip and a DRAM FIFO.
I tried to compile it before installing any patch, after installing the DRAM patch, and after installing both patches and always got a Xilinx error after ~10 minutes compile time. The error summary shown above and the attached Xilinx log are from compiling with both patches installed.
It compiled correctly on our older system:
Hardware:
NI PXIe-1082 Chassis
NI PXIe-8133 Embedded controller
NI PXIe-7965R FPGA FlexRIO FPGA module
NI 5761 250 MS/s 14 bit Analog input digitizer
Installed software:
Labview2011version10.0.0
LabviewFPGAmodule10.0.0
FPGAcompilationtools (Xilinx11_5)
NIFlexRIOAdapterModuleSupport2.1.0
NI-RIO3.5.1 (FlexRIO1.5.0)
XilinxDRAMcompilationbugfixpatchfromNIarticleid5E4FNCDP
Any help / suggestions greatly appreciated,
Fabrizio
Attachments:
XilinxLog.txt ‏1482 KB

Hi Torpedotown,
Can you tell me what version of FlexRIO Adapter Module Support you are using?
The 5761 Low Speed CLIP has a constraint that doesn't work properly with some versions of the compilation tools. In order to solve this you should be able to upgrade to our latest version of FAM support, or go change the constraint manually.
For the latest version of FAM support, go to http://ni.com/info and enter code "famsoftware"
If you've modified constraint files before and feel comfortable doing it yourself, let me know and I can provide you with the details on how to do that.
Thanks!
National Instruments
FlexRIO & R-Series Product Support Engineer

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

FlexRIO DRAM problem in Labview FPGA 2010

Hello,
I am just switching from Labview FPGA 2009 to Labview FPGA 2010 and I am having compilation problems with very simple projects that shouldn't fail to compile.
I am using a FlexRIO 7965R board as a target. Initially, I just wanted to recompile a project that was working fine under Labview FPGA 2009. When it failed, I drastically
simplified it to isolate the source of error. I ended up with what is attached. In this very simple VI I just write some values into DRAM banks in one timed loop, read them out in another and send them through a Target to Host DMA FIFO. Both loops are quite slow running at only 40 MHz. Previously, I was able to compile VIs with DRAM clip nodes in timed loops running at 100 MHz without any problems.
The compilation fails with this summary:
"Compilation
failed due to resource overmapping"
although it should fit easily.
The error is definitely related to DRAM. This s what Xilinx log says:
"ERRORlace:543
- This design does not fit into the number of slices available in this device
due to the complexity of
   the design and/or constraints.
   Unplaced instances by type:
     IDELAYCTRL    21 (48.8) "
Then it lists these instances (about 20):
   0. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate0
   1. IDELAYCTRL
Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate1
   2. IDELAYCTRL Puma20DramMainx/GenBank0or1Mig.u_ddr2_idelay_ctrl/u_idelayctrl_MapLib_replicate2
Both DRAM banks are configured with the clip node for 128-bit FIFO version v1.1.0. I also tried using the legacy version v1.0.0 but it didn't make any difference.
It looks like I have some configuration problems I can't identify or there is something wrong with the DRAM clip node in Labview FPGA 2010.
Any ideas on what could be happening here? Any help would be much appreciated.
Regards,
Ivan
Attachments:
flexrio_dram_test.lvproj ‏157 KB
flexrio_dram_test_fpga.vi ‏124 KB

Hello Ivan,
It looks like in your project you are using both the NI 5761 adapter module and DRAM. We have seen a few cases where certain combinations of DRAM, adapter modules, and FlexRIO FPGA targets in LabVIEW FPGA 2010 have caused some resource overmapping errors of the IODelayCtrl components used in the adapter module and DRAM CLIPs. Due to a bug, certain constraints inside of the CLIP cores are misinterpreted by the ISE compiler causing this overmap error when you switch to LabVIEW FPGA 2010.
This was reported to R&D (# 258076) for further investigation and to create a long term fix. In the meantime, for this specific issue please use the following knowledgebase article to apply a patch to your FlexRIO fixed logic files. This patch updates some of the constraints used by the DRAM to ensure that the Xilinx compiler can properly interpret them. There are more details on your issue in the knowledgebase as well.
Knowledgebase 5E4FNCDP: Error, “Compilation Failed Due to Resource Overmapping,” When Using NI FlexR...
If you do run into any other issues regarding IODelayCtrl components, feel free to reply to this forum topic to let me know about them.
Regards,
Browning G
FlexRIO R&D

Why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?

Dear Friends,
Since I have started using LABVIEW FPGA, I got too many questions in my mind looking for answers!
1-      Does anybody can tell me “why should I adopt LABVIEW FPGA as a tool for developing my FPGA projects?”
I mean there are many great tools in this field (e.g. Xilinx ISE, ….); what makes LABVIEW FPGA the perfect tools that can save my time and my money?
I’m looking for a comparison can show the following points:
·         The Code size and speed optimization.
·         Developing time.
·         Compiling time.
·         Verifying time.
·         Ability to developing in future.
·         …etc.. 2-
I’ve Spartan-3E kit, I’m so glad that LABVIEW support this kit; I do enjoyed programming the kit using LABVIEW FPGA, but there are too many obstacles!
The examples come with Spartan-3E driver don't cover all peripherals on board (e.g. LAN port is not covered)! There is a declaration at NI website which is "LabVIEW FPGA drivers and examples for all on-board resources" Located at: http://digital.ni.com/express.nsf/bycode/spartan3eI don’t think that is true!
Anyway, I will try to develop examples for the unsupported peripherals, but if the Pins of these peripherals are not defined in the UCF file, the effort is worthless! The only solution in this case is to develop VHDL code in ISE and use it in Labview FPGA using HDL node!?
3-      I wonder if NI has any plan to add support for Processor setup in Labview FPGA (Like we do in EDK)?
4-      I wonder if NI has any plan to develop a driver for Virtex-5 OpenSPARC Evaluation Platform ?http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,599&Prod=XUPV5
Thnaks & regards,Walid
Solved!
Go to Solution.

Thanks for your questions and I hope I can answer them appropriately
1. LabVIEW FPGA utilizes the intuitive graphical dataflow language of LabVIEW to target FPGA technology. LabVIEW is particularly nice for FPGA programming because of its ability to represent parallelism inherent to FPGAs. It also serves as a software-like programming experience with loops and structures which has become a focus of industry lately with C-to-gates and other abstraction efforts. Here are some general comparison along the vectors you mentioned
Code Size and speed optimization - LabVIEW FPGA is a programming language. As such, one can program badly and create designs that are too big to fit on a chip and too slow to meet timing. However, there are two main programming paradigms which you can use. The normal LabVIEW dataflow programming (meaning outside a single-cycle loop) adds registers in order to enforce dataflow and synchronization in parity with the LabVIEW model of computation. As with any abstraction, this use of registers is logic necessary to enforce LabVIEW dataflow and might not be what an expert HDL programmer would create. You trade off the simplicity of LabVIEW dataflow in this case. On the other hand, when you program inside a Single-Cycle timed loop you can achieve size and speed efficiencies comparable to many VHDL implementations. We have had many users that understand that way LabVIEW is transformed to hardware and program in such a way to create very efficient and complex systems.
Development Time - Compared to VHDL many of our users get near infinite improvements in development time due to the fact that they do not know (nor do they have to know) VHDL or Verilog. Someone who knows LabVIEW can now reach the speeds and parallelism afforded by FPGAs without learning a new language. For harware engineers (that might actually have an alternative to LabVIEW) there are still extreme time saving aspects of LabVIEW including ready-made I/O interfaces, Simple FIFO DMA transfers, stichable IP blocks, and visualizable parallism. I talk to many hardware engineers that are able to drastically improve development time with LabVIEW, especially since they are more knowledgable about the target hardware.
Compilation Time - Comparable to slightly longer to due to the extra step of generating intermediate files from the LabVIEW diagram, and the increased level of hierarchy in the design to handle abstraction.
Verification Time - One of our key development initiatives moving forward is increased debugging capabilities. Today we have the abilities to functionally simulate anything included in LabVIEW FPGA, and we recently added simluation capabilities for Imported IP through the IP Integration node on NI Labs and the ability to excite your design with simulated I/O. This functional simualation is very fast and is great for verification and quick-turn design iteration. However, we still want to provide more debugging from the timing prespective with better cycle-accurate simulation. Although significantly slower than functional simulation. Cycle-accuracy give us the next level of verification before compilation. The single cycle loop running in emulation mode is cycle accurate simluation, but we want more system level simulation moving forwrad. Finally, we have worked to import things like Xilinx chipscope (soon to be on NI Labs) for on-chip debugging, which is the final step in the verification process. In terms of verification time there are aspects (like functional simulation) that are faster than traditional methods and others that are comparable, and still other that we are continuing to refine.
Ability to develop in the future - I am not sure what you mean here but we are certainly continuing to activiely develop on the RIO platform which includes FPGA as the key diffentiating technolgoy.  If you take a look at the NI Week keynote videos (ni.com/niweek) there is no doubt from both Day 1 and Day 2 that FPGA will be an important well maintained platform for many years to come.
2. Apologies for the statement in the document. The sentence should read that there are example for most board resources.
3. We do have plans to support a processor on the FPGA through LabVIEW FPGA. In fact, you will see technology on NI Labs soon that addresses this with MicroBlaze.
4. We do not currently have plans to support any other evaluation platforms. This support was created for our counterparts in the academic space to have a platform to learn the basics of digital design on a board that many schools already have in house. We are currently foccussing on rounding out more of our off-the-shelf platform with new PCI Express R Series boards, FlexRIO with new adapter modules, cRIO with new Virtex 5 backplanes, and more.
I hope this has anwered some of the questions you have.
Regards
Rick Kuhlman | LabVIEW FPGA Product Manager | National Instruments | ni.com/fpga
Check out the FPGA IPNet for browsing, downloading, and learning about LabVIEW FPGA IP Cores

LabView fpga VHDL code and compiler

Hello,
I'm in the project where we would like to use NI hardware (more likely cRIO system). With NI hardware we will read/wright several AI/AO and DIO and perform some math and controls on the result of readings. We are planning to design FPGA code for project, but we are thinking about implement all data processing and control logic in VHDL and link it with AI, AO and DIO with help CLIP or IP Integration Node as explained in this : "white-paper": http://www.ni.com/white-paper/7444/en/
Mentioned above paper explain how to implement VHDL code in LabVIEW FPGA VI using CLIP or IP Integration Node, but the topic that is not highlight explicitly is how these construction CLIP and IP Integration Node will be handled by Compiler. The main reason for such approach (VHDL linked with part that read/write into hardware AI AO and DIO) we expect that our VHDL code will be handled by LabVIEW compiler without modification and passed to Xilinx Compiler synthesis as is (path for Compile process I've taken from here: http://www.ni.com/white-paper/9381/en/ ), so we will be able at some level bypass the intermediate process of compilation and get almost the same result as if we design pure VHDL code and use Xilinx ISE for Synthesis Mapping and Bit File generation.
Will this approach work? I was not able to find any documents that explain the Compiler behavior and confirm that VHDL code handled untouched or will modified, does such document exist?
Note. I've requested official assistance from NI support on topic above, but I would like to post this question on forum hoping get more feedback.

Hello RangerOne,
There won't be any modications to the internal logic of the VHDL that you implement in the IP integration node. Though I've seen developers unfamiliar with LabVIEW FPGA get tripped up on the synchronization registers that LabVIEW FPGA inserts into the code around the integration node. Learning where and why these syncrhonization registers are inserted has in my experience always resolved this issue. These two help documents do a good job of explaining the 'where and why' of synch registers when the enable chain is present, or when working with IO inside of a SCTL.
With regards to the stability of LabVIEW FPGA, I would second Daniel's sentiments. What about the known issues list conveys instability and risk? As a point of comparison, here are the known issues for ISE 14.x.
If you are looking to minimize risk, I would recommend developing the critical logic in the development enviroment in which you are comfortable setting up a comprehensive test bench since testing the code is the only way to truly verify its functionality. For me this would be LabVIEW FPGA as it has excellent trouble shooting tools and I've been developing in it for quite some time. Perhaps you're more familiar with ISE than LabVIEW FPGA and that is the source of your trepidation? If that is the case then you may find the High Performance FPGA Developers Guide a good read. You may also find a few of the case studies on our website reassuring since they demonstrate other teams successfully implementing a solution using LabVIEW FPGA. Here's one that used LabVIEW FPGA in conjnction with VHDL IP similiar to what you are doing.
National Instruments
FlexRIO Product Support Engineer

How can I install (download) a Labview FPGA code onto Altera FPGA chip using Labview FPGA module?

Hi there
Guys i'm a very new labview user (PhD student), my project is about ( design and implementation of a high speed-yet sophisticated system using Labview environment then install this project's code (using Labview FPGA module) onto Altera-made FPGA chip).
so kindly, can any body help me in this?...is there any way to connect labview with Altera FPGA?...please anything would be said 'd be of great benifits
thanks a lot in advance.

as previously mentioned, labview fpga only supports national instruments targets utilizing xilinx fpgas. the hdl generated by labview fpga is encrypted and cannot be used to synthesize a design outside the labview fpga design flow.
however, if you must use labview for your project, it might be possible for you to design the system in labview and use one of the labview embedded modules ( http://www.ni.com/embedded )to generate c code which you can then port to systemc and compile for the altera fpga. i'm not saying it will be easy, but it should be possible.

Labview FPGA for beginners.

Hello.
I have no idea what labview is and how to work with this. I have had some experience with Xilinx 12.1 EDK (microblaze and VHDL).
I tried to install labview and labview fpga module. It asked for some drivers and I continued, the program said that it will ask for the drivers later.
But, beside that, do you have any training flow to suggest? Should I start with labview or is it not necessary? After that, should I start with CVI or FPGA? I am confused. Any help is welcomed!
Thanks,
Bill.

See this video's to get start with labVIEW and more video's you can find in youtube. Also, get in touch with forum especially about FPGA questions or read the history question targeting to your design area.
http://zone.ni.com/devzone/cda/tut/p/id/7466
I never use FPGA codes or concepts in labVIEW but I am looking to learn now.

Labview FPGA called another software component

Hi
I am trying to compile my FPGA code which has previously compiled. I get this error.
"Labview FPGA called another software component, and that component returned the following error:
Error Code: -52009
NI Platform Services: The requested resource has been marked for deletion and is rejecting new requests."
What is this error code?

Hi,
I've been looking in to this for you today - unfortunately, that seems to be a really rare error code which doesn't come up very often on our systems, so there's no quick fix that I can find.
A couple of options:
1) Have you made any changes to the code recently, in terms of updating it from an earlier version of LabVIEW? If so, it may be worth mass compiling your project up to the latest version in case there are references to software components which no longer exist.
2) It's probably worth a try repairing your LabVIEW, FPGA and RIO drivers installations from disk, as described here: http://digital.ni.com/public.nsf/allkb/FE6B641E86E55AF2862576DE00038001?OpenDocument
This could be due to some kind of missing or corrupted component in, for example, the Xilinx Tools
3) Are you referencing any kind of external software, such as DLLs or third party instruments, in your file?
4) What hardware are you using?
Please let me know how you get on with these queries.
Best wishes,
Chiara A
Applications Engineer with NI UK & Ireland

Labview fpga development board

hi all
can i programme my own development board having xillinx fpga using labview fpga .. or lab view fpga can only be used by national instruments hardware ?
Regards

Just to reiterate what was already said, The LabVIEW FPGA generates VHDL code that can not be used or downloaded into non-NI hardware, even if it uses the same Xilinx FPGA.
That being said, there is one board that you can use that is not National Instruments, Xilinx SPARTAN-3E XUP Starter Kit
Regards,
Andrew Eddleman
National Instruments
RIO Embedded Hardware PSE
CompactRIO Developers Guide

Labview fpga module Spartan 6 LX9 FPGA

Does Spartan 6 LX9 FPGA supported in labview FPGA module ?

varunme,
The only FPGA targets that can be programmed with LabVIEW FPGA are National Instruments FPGA products (cRIO, sbRIO, R-Series, FlexRIO, etc) and the Xilinx Spartan 3E XUP board. Unfortunately, LabVIEW FPGA doesn't support third party devices containing the LX9 FPGA.
-Nick-
Nick C | Staff LabVIEW Platform Product Support Engineer | National Instruments

Labview fpga vs xilinx ise

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