Is AES supported in 1.4.1
Hi is there a reason why I cannot use AES with 1.4.1 and a Mac OSX 1.2.8 machine?
DES and Blowfish worked so far.
What gives?
Thanks in advance
If 1.4.2 is available for the Mac, then yes - other wise, no.
You can use a different Provider - try bouncycastle.org, should work just fine.
Grant
Similar Messages
-
Hi all,
is there any function that specifies key size "secret key" used in AES cryptographic algorithm? if not which key size is supported?
thanks alot.Hi again,
i ve tried what you have told me but it gave me error ERROR: java.security.InvalidKeyException: Illegal key size or default parameters
here is the code
SecureRandom sprng = SecureRandom.getInstance("SHA1PRNG");
KeyGenerator key = KeyGenerator.getInstance("AES");
//key.init(sprng);
key.init(192, sprng);
SecretKey encKey = key.generateKey();
symmetricKey=encKey;
Cipher encAES = Cipher.getInstance("AES");
encAES.init(Cipher.ENCRYPT_MODE, encKey);
encMsg=encAES.doFinal(message.getBytes());can any body help me plz! -
Hi,
Does anyone know when SunJCE will support AES. I tried to experiment with 1.4.2 version and didnt see any support. However IBM JCE ( comes with the 1.4.2 version) seems to have support for it.
Thanks.
Sunitha.sorry!
Actually, I was trying out with 1.4.1 jvm and hence AES wasnt working.
However, sun jce in 1.4.2 AES is supported.
Sunitha. -
Is it available an AES256 encryption support for the SRA Gateway Service?
Otherwise, is it possible to plug-in a custom/self-made cipher?
Finally (this is an RFE) it will be interesting if the Gateway could do the encryption job by using openssl APIs instead of the NSS ones, so that one could use his own openssl-based engine.Hi Walt, thank you for the feedback and for using the Remote Desktop app.
We look at the user feedback in the Store and other site and know how important Gateway is to Remote Desktop, notably so on a phone.
This is on our list of scenarios to enable, look for it in a future update later this year.
Thanks,
David Belanger
This post is "AS IS" and confers no rights. -
I am currently attempting to activate IPSecurity on Solaris and I am having a host of issues. I am hoping someone on the forums have done this before.
Here are the steps that I have figured out:
1) Create Certificates and add them into the database: I am fairly certain that this has been done correctly since when the in.iked daemon comes up it reads in my CA certificate and my server certificate that I have created.
2) Edit the /etc/inet/ike/config file. I have edited this file but there is an odd thing here. Looking at the man page it says that I should be able to do use AES for the phase 1 SA. However when I use the key word for the aes it tells me it is an error. <Question> Is the AES support only on 10? Is there away I can tell the version of the in.iked daemon I am working with?
3) Activate the in.iked server with the config file. I have done this and used the -p2 -d options so I can see the log file that goes with it.
4)Update the /etc/inet/ipsec.init file: I have done this but here is another instance that things do not make sense. I create a phase 2 proposal devoid of all encryption algorithms and the default one came up. It only had AES and Blowfish. There was no Triple DES option available even though in the man page is there. <question> how do I get the version number of the ipsecconf command.
5)I then use the ipsecconf command to suck in the ipsec.init profile. I have done this successfully with AES and can do a list display.
Usage<<<< I attempt to run a traffic from my solaris to my partner machine that matches the phase 2 traffic descriptors however when the traffic arrives it is not encrypted and the solaris did not attempt to negotiate a tunnel.
When I attempt to initiate a VPN from the other side all I get is parameter mismatch on the Solaris side however the parameters that I have configured all seem to match.
<Questions>
1) Is there some better messages available above -p2 -d
2) Is there a way to initiate a phase 1 negotiation on the SA. ikeadm command does not seem to have that.
3) Is there a service that I have to activate to start the IPSecurity pieces?http://www.sun.com/servers/coolthreads/t2000/specs.xml
no.
Darren -
Hi all,
Just looking at the AES standard, or wiki of it
http://en.wikipedia.org/wiki/Advanced_Encryption_Standard
It mentions that AES supports the following (in the notes just at the bottom of the web page)
Key sizes of 128, 160, 192, 224, and 256 bits are supported by the Rijndael algorithm, but only the 128, 192, and 256-bit key sizes are specified in the AES standard.
Block sizes of 128, 160, 192, 224, and 256 bits are supported by the Rijndael algorithm, but only the 128-bit block size is specified in the AES standard.
What does the WLCs use for an AES key size when you enable a WPA2 policy with AES encryption?
Many thx
Ken128 bits was supported on the autonomous code, so I'm sure the LWAPP solution also uses 128 bits with three possible key lengths 128, 192 and 256 bits.
-
No AES-NI Instructions on T410 / i5 560M
Hello,
Has anyone else had issues with AES-NI instructions missing on the T410? I just got mine, with an i5 560M, and neither TrueCrypt nor CPU-Z see the AES instructions as a capability for the chip. I've seen very little online about this issue, so a couple of things:
1. The i5 560M definitely supports AES-NI. Intel's site, and everyone else's, says so. The whole i5 line does.
2. I've tried this in both 64-bit and 32-bit Windows.
3. CPU-Z definitely has support for detecting AES-NI in processors that support it. I've even seen a screenshot of an i5 560M showing AES instructions in CPU-Z. Mine, however, doesn't show AES support. TrueCrypt confirms.
4. There are no settings in the BIOS pertaining to AES instructions.
This is a pretty big deal for me--AES-NI offers a huge performance benefit for those using encrypted drives through software like TrueCrypt.
I expect this is a BIOS bug, but does anyone have any other info?
Thanks!Hello mate,
The wole i5 line doesn't support AES-NI but the 560M does.
What version of TrueCrypt are you using ? TrueCrypt support AES from the 7.0
Knowledge is of two kinds. We know a subject ourselves, or we know where we can find information on it.
ThinkPad T510 4313-CTO Windows 8 x64 - Intel Core i7-620M - NVIDIA NVS 3100M - 8GB RAM - 240GB SSD- Intel Centrino Ultimate-N 6300 - Gobi 2000.
ThinkPad Helix 3697-CTO Windows 8.1 x64 - Intel Core i7-3667U - Intel HD Graphics 4000 - 8GB RAM- 256GB SSD - Intel Centrino Advanced-N 6205 - Ericsson C5621gw -
KeyAgreement can't generate AES Cipher
Hi,
I tried to generate a SecretKey out of a completed Diffie-Hellamn KeyAgreement but it doesn't work.
If I use keyAgreement.generate("DESede"); with J2SE 1.4.2 it functions properly, but if I use "AES" instead it throws a NoSuchAlgorithmException.
Does anyone know how to use AES for Secret generation with a KeyAgreement?
Thanks
SurfaczerThe diffie hellmen implementation must support the creation of AES
keys. Just because a provider supports AES does not mean their DH
implementation does and chances are that is what is wrong. Sun's
DH impl explicitly checks the alg name and does a if / else if
operation to create appropriate sized keys. AES supports variable
size keys. So what should the alg name AES create? And now you
see the crux of the problem. AES has several OIDs which define
AES in various modes of operation and with various key sizes.
Those might more accurately define the key size desired but there
is a problem. Sun's if / else if doesn't really fit that model...
So I will bet that they just haven't implemented it yet primarily
because they need to define the algorithm names they will support.
For example maybe AES-128 or aes128 or something like that... Of
course it could just be an oversight as well. Someone would have
to go back and modify their existing DH code to add AES support
and maybe they forgot. Maybe you should post a bug report and see
what they say! -
Two days ago my phone locked up and when I could access again, my contact list was only a few names and email addresses. ALL phone numbers wiped from the phone. I have been using google sync for three years to sync contact and calendar to gmail and then sync gmail to iphone, and it has been seemless. I would think this was the problem, however the contacts and phone numbers that were added directly the phone are no longer on the phone either....which point to a phone problem.
I went home, to update but ended up having to "restore" from backup, which I did. The contacts were visible for less than 24 hours, but then disappeared again the next day. I have tried forums for google sync as that would solve a large amount of the contacts, but I still can't seem to find a solution for the other contacts added directly to the phone.
are there any new glitches/issues with the iOS 6 that cause this problem?
phone is 3GS.
thanks.Do the numbers still exist in your google contacts?
Google recently terminated support for new configurations of gmail using Exchange Active Sync for unpaid accounts. In theory, existing configurations will continue to work, but there have been some problem reports.
I've seen several mentions of the problem you describe in the last few days and so far, they've gone unresolved as far as I can tell. The root cause may be in google's termination of AES support.
Facebook contact sync may also be a suspect. -
Hyper-V not installing on Windows 8.1
Hi
I can't activate the Hyper-V feature of Windows 8.1. Whenever I enable the feature all goes well, I reboot when prompted. But after the reboot Hyper-V is not installed - it's shown as not installed in "Turn Windows feature on and off".
The Windows Setup log has an information event (ID 11) "Update Microsoft-Hyper-V of package Microsoft-Hyper-V-ClientEdition-Package failed to be turned on. Status: 0x800f0922."
I tried DISM.exe /Online /Cleanup-Image /RestoreHealth, but that made difference.
I also tried activating the feature through DISM, but no joy.
Finally, I tried changing my SSD to a spare I had, and doing a fresh Windows 8.1 install on the new SSD, but Hyper-V still doesn't install.
I have a i7 CPU, and virtualization is enabled in the BIOS.
RoyOutput from Coreinfo -v:
Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz
Intel64 Family 6 Model 60 Stepping 3, GenuineIntel
Microcode signature: 0000001A
HTT *
Hyperthreading enabled
HYPERVISOR -
Hypervisor is present
VMX *
Supports Intel hardware-assisted virtualization
SVM -
Supports AMD hardware-assisted virtualization
X64 *
Supports 64-bit mode
SMX -
Supports Intel trusted execution
SKINIT -
Supports AMD SKINIT
NX *
Supports no-execute page protection
SMEP *
Supports Supervisor Mode Execution Prevention
SMAP -
Supports Supervisor Mode Access Prevention
PAGE1GB *
Supports 1 GB large pages
PAE *
Supports > 32-bit physical addresses
PAT *
Supports Page Attribute Table
PSE *
Supports 4 MB pages
PSE36 *
Supports > 32-bit address 4 MB pages
PGE *
Supports global bit in page tables
SS *
Supports bus snooping for cache operations
VME *
Supports Virtual-8086 mode
RDWRFSGSBASE *
Supports direct GS/FS base access
FPU *
Implements i387 floating point instructions
MMX *
Supports MMX instruction set
MMXEXT -
Implements AMD MMX extensions
3DNOW -
Supports 3DNow! instructions
3DNOWEXT -
Supports 3DNow! extension instructions
SSE *
Supports Streaming SIMD Extensions
SSE2 *
Supports Streaming SIMD Extensions 2
SSE3 *
Supports Streaming SIMD Extensions 3
SSSE3 *
Supports Supplemental SIMD Extensions 3
SSE4a -
Supports Streaming SIMDR Extensions 4a
SSE4.1 *
Supports Streaming SIMD Extensions 4.1
SSE4.2 *
Supports Streaming SIMD Extensions 4.2
AES *
Supports AES extensions
AVX *
Supports AVX intruction extensions
FMA *
Supports FMA extensions using YMM state
MSR *
Implements RDMSR/WRMSR instructions
MTRR *
Supports Memory Type Range Registers
XSAVE *
Supports XSAVE/XRSTOR instructions
OSXSAVE *
Supports XSETBV/XGETBV instructions
RDRAND *
Supports RDRAND instruction
RDSEED -
Supports RDSEED instruction
CMOV *
Supports CMOVcc instruction
CLFSH *
Supports CLFLUSH instruction
CX8 *
Supports compare and exchange 8-byte instructions
CX16 *
Supports CMPXCHG16B instruction
BMI1 *
Supports bit manipulation extensions 1
BMI2 *
Supports bit manipulation extensions 2
ADX -
Supports ADCX/ADOX instructions
DCA -
Supports prefetch from memory-mapped device
F16C *
Supports half-precision instruction
FXSR *
Supports FXSAVE/FXSTOR instructions
FFXSR -
Supports optimized FXSAVE/FSRSTOR instruction
MONITOR *
Supports MONITOR and MWAIT instructions
MOVBE *
Supports MOVBE instruction
ERMSB *
Supports Enhanced REP MOVSB/STOSB
PCLMULDQ *
Supports PCLMULDQ instruction
POPCNT *
Supports POPCNT instruction
LZCNT *
Supports LZCNT instruction
SEP *
Supports fast system call instructions
LAHF-SAHF *
Supports LAHF/SAHF instructions in 64-bit mode
HLE *
Supports Hardware Lock Elision instructions
RTM *
Supports Restricted Transactional Memory instructions
DE *
Supports I/O breakpoints including CR4.DE
DTES64 *
Can write history of 64-bit branch addresses
DS *
Implements memory-resident debug buffer
DS-CPL *
Supports Debug Store feature with CPL
PCID *
Supports PCIDs and settable CR4.PCIDE
INVPCID *
Supports INVPCID instruction
PDCM *
Supports Performance Capabilities MSR
RDTSCP *
Supports RDTSCP instruction
TSC *
Supports RDTSC instruction
TSC-DEADLINE *
Local APIC supports one-shot deadline timer
TSC-INVARIANT *
TSC runs at constant rate
xTPR *
Supports disabling task priority messages
EIST *
Supports Enhanced Intel Speedstep
ACPI *
Implements MSR for power management
TM *
Implements thermal monitor circuitry
TM2 *
Implements Thermal Monitor 2 control
APIC *
Implements software-accessible local APIC
x2APIC *
Supports x2APIC
CNXT-ID -
L1 data cache mode adaptive or BIOS
MCE *
Supports Machine Check, INT18 and CR4.MCE
MCA *
Implements Machine Check Architecture
PBE *
Supports use of FERR#/PBE# pin
PSN -
Implements 96-bit processor serial number
PREFETCHW *
Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended).
Logical to Physical Processor Map:
**------ Physical Processor 0 (Hyperthreaded)
--**---- Physical Processor 1 (Hyperthreaded)
----**-- Physical Processor 2 (Hyperthreaded)
------** Physical Processor 3 (Hyperthreaded)
Logical Processor to Socket Map:
******** Socket 0
Logical Processor to NUMA Node Map:
******** NUMA Node 0
No NUMA nodes.
Logical Processor to Cache Map:
**------ Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------ Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------ Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
******** Unified Cache 1, Level 3, 8 MB, Assoc 16, LineSize 64
--**---- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**---- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**---- Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
----**-- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**-- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**-- Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64
------** Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------** Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------** Unified Cache 4, Level 2, 256 KB, Assoc 8, LineSize 64
Logical Processor to Group Map:
******** Group 0 -
Trouble Installing Windows 8.1 32bit on a Pentium 4 box.
I am trying to install Windows 8.1 32bit on a Pentium 4 box but failed.
"Your PC needs to restart. Please hold down the power button. Error Code 0x0000000A"
Can somebody tell me what is wrong or my hardware is not supported.
I did a coreinfo dump and it contains the information below:
Intel(R) Pentium(R) 4 CPU 2.40GHz
x86 Family 15 Model 2 Stepping 9, GenuineIntel
Microcode signature: 0000002E
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 - Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX - Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB - Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 - Supports Streaming SIMD Extensions 3
SSSE3 - Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 - Supports Streaming SIMD Extensions 4.1
SSE4.2 - Supports Streaming SIMD Extensions 4.2
AES - Supports AES extensions
AVX - Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE - Supports XSAVE/XRSTOR instructions
OSXSAVE - Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 - Supports CMPXCHG16B instruction
BMI1 - Supports bit manipulation extensions 1
BMI2 - Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR - Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ - Supports PCLMULDQ instruction
POPCNT - Supports POPCNT instruction
LZCNT - Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF - Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM - Supports Performance Capabilities MSR
RDTSCP - Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT - TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST - Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 - Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID * L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW - Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 00000002 (Basic), 80000004 (Extended).
Logical to Physical Processor Map:
* Physical Processor 0
Logical Processor to Socket Map:
* Socket 0
Logical Processor to NUMA Node Map:
* NUMA Node 0
Logical Processor to Cache Map:Hi mgallego,
Which step did the error start to occur ?Have you tried to install it again to have a check ?As the information stated, we can restart the machine to have a check.
Here is a link for reference of the requirements of the Windows 8.1 .
System requirements
http://windows.microsoft.com/en-HK/windows-8/system-requirements
There may be a hardware issue here, it is also recommended to look for help from the manufacturer for help.
Best regards
Please remember to mark the replies as answers if they help, and unmark the answers if they provide no help. If you have feedback for TechNet Support, contact [email protected] -
WPA - Enterprise oddities, any suggestions?
We have a WPA/WPA2 Enterprise (PEAP) network and are having trouble with our users iPhones. (They work fine on the open network SSID, but would like to migrate to the somewhat more secure WPA or WPA2 model.)
Apple iPhones 2.2.1 [5H111]
Apple iPods 2.2.1 [5H11a]
Cisco APs 12.3(8)JA2 or 12.3(3)JEC2 (same results) (WPA TKIP and AES support enabled)
OUR STANDARD AP CONFIG: and our results
OPEN SSID (hidden) = iPhones works fine
WPA2 SSID (broadcast) = iPhones fail to connect (occasionally after certificate)
(BUT iPods work just fine!, as does Ubuntu, XP, etc.)
TESTED config 1: (but this setup is incompatible with our network design)
OPEN SSID (broadcast) = iPhone works
WPA2 SSID (broadcast) = iPhone works
TESTED config2: (not desired configuration)
OPEN SSID (broadcast) = iPhone Works
WPA2 SSID (hidden) = iPhone Works
The Standard config needs to be implemented and supported for a variety of reasons. (We use .1X to move clients to various VLANs behind that SSID so can't enable multi-broadcast on our equipment.) We need to broadcast our WPA network SSID instead of the OPEN SSID, but are having issues.
As this problem ONLY seems to impact our iPhone users, and not iPods, (with the same version of software) suspect there may be a simple setting on the phones or APs that we are missing. Anyone else ran into this and have any pointers?We have also noted the very same problem with 1G iPod Touch. (Several users pointed this out after deployment.)
We have implemented a work-around by having a WPA2#2 SSID as a hidden so these iPhones and iPods can attach to the network. This now allows them to associate without a problem.
However on the hidden ID they seem to connect/disconnect from the network, and may require a user to go to the networks area to get connected after the device is left alone for some time. -
Log Name: Microsoft-Windows-Hyper-V-VMMS-Admin
Source: Microsoft-Windows-Hyper-V-VMMS
Date: 16.9.13 13:03:39
Event ID: 15350
Level: Error
Description:
The virtualization infrastructure driver (VID) is not running.
<Provider Name="Microsoft-Windows-Hyper-V-VMMS" Guid="{6066F867-7CA1-4418-85FD-36E3F9C0600C}" />
I encountered a file corruption problem in August, about the time of the monthly Windows Updates. System File Checker was unable to resolve the problem so I did a Repair Install of Windows 8. This seemingly corrected the file corruption. I have
not been able to determine what caused the file corruption but it left the system with a number of unresolved errors and warnings in Event Viewer, which I am working through. I should say that these errors do not seem to be preventing the computer from
working but I like to try to understand and resolve Event Viewer errors.
The error above is one of several recurring errors relating to Hyper-V. My understanding is that Hyper-V is concerned with using virtual devices but none have been set up on this computer. For this reason I am wondering why the system is expecting
virtualization infrastructure driver (VID) to be running. The related services are set to Manual and there are no obvious problems indicated in Device Manager. I have looked in the BIOS but I was unable to identify
any reference to VMX.
Can anyone please explain how I might eliminate these error reports?
TIA, GerryI have been on hyperV for last many years and stumped on this one.
I'm seeing the same issue on a fresh install of Windows 8.1 Enterprise.
Unable to start VM.
Virtual machine 'Test' could not be started because the hypervisor is not running (Virtual machine ID 891693BC-8764-47AE-B885-195FB6079DD2). The following actions may help you resolve the problem: 1) Verify that the processor of the physical computer has
a supported version of hardware-assisted virtualization. 2) Verify that hardware-assisted virtualization and hardware-assisted data execution protection are enabled in the BIOS of the physical computer. (If you edit the BIOS to enable either setting,
you must turn off the power to the physical computer and then turn it back on. Resetting the physical computer is not sufficient.) 3) If you have made changes to the Boot Configuration Data store, review these changes to ensure that the hypervisor is
configured to launch automatically.
checked below:
1. VT Enabled in BIOS already
2. Boot settings Hypervisorlaunchtype set to auto
3. Hard power off & Power On multiple times.
Saw the error in Event log:
The virtualization infrastructure driver (VID) is not running.
Landed on this post .. FOund nothing else..
1. Remove the role. reboots 2 times.
2. Readded the role. reboots 2 times.
No change. Was wondering if this is related to SLAT in anyway. Some more info:
1. My previous working setup was a Windows 8 in place upgrade -> Windows 8.1 . HyperV was working fine.
2. Processor is Processor Intel(R) Core(TM) i7 CPU Q 740 @ 1.73GHz, 1734 Mhz, 4 Core(s), 8 Logical Processor(s)
3. Laptop is a Dell E6510
Fired up CoreiInfo - > Shows I have SLAT and Hypervisor enabled
Coreinfo v3.2 - Dump information on system CPU and memory topology
Copyright (C) 2008-2012 Mark Russinovich
Sysinternals - www.sysinternals.com
Intel(R) Core(TM) i7 CPU Q 740 @ 1.73GHz
Intel64 Family 6 Model 30 Stepping 5, GenuineIntel
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX * Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
EM64T * Supports 64-bit mode
SMX * Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX * Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB - Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES - Supports AES extensions
AVX - Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE - Supports XSAVE/XRSTOR instructions
OSXSAVE - Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 - Supports bit manipulation extensions 1
BMI2 - Supports bit maniuplation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLULDQ - Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instruction
DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL * Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM * Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST * Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Logical to Physical Processor Map:
**------ Physical Processor 0 (Hyperthreaded)
--**---- Physical Processor 1 (Hyperthreaded)
----**-- Physical Processor 2 (Hyperthreaded)
------** Physical Processor 3 (Hyperthreaded)
Logical Processor to Socket Map:
******** Socket 0
Logical Processor to NUMA Node Map:
******** NUMA Node 0
Logical Processor to Cache Map:
**------ Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------ Instruction Cache 0, Level 1, 32 KB, Assoc 4, LineSize 64
**------ Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
******** Unified Cache 1, Level 3, 6 MB, Assoc 12, LineSize 64
--**---- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**---- Instruction Cache 1, Level 1, 32 KB, Assoc 4, LineSize 64
--**---- Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
----**-- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**-- Instruction Cache 2, Level 1, 32 KB, Assoc 4, LineSize 64
----**-- Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64
------** Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------** Instruction Cache 3, Level 1, 32 KB, Assoc 4, LineSize 64
------** Unified Cache 4, Level 2, 256 KB, Assoc 8, LineSize 64
Logical Processor to Group Map:
******** Group 0
Could I try Anything else ?
Regards Ravindran Keshavan MCSA |MCTS (SCOM)| ITILv2 -
Windows 8 - Can My PC Run IT? Check My CPU Coreinfo Report
Hi Dear Friends,
Can anyone tell me can my CPU Run Windows 8 x86 and Windows 8 x64 thanX in advance, my CPU Coreinfo Report is here:
Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright (C) 2008-2014 Mark Russinovich
Sysinternals - www.sysinternals.com
Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright (C) 2008-2014 Mark Russinovich
Sysinternals - www.sysinternals.com
Intel(R) Pentium(R) 4 CPU 2.60GHz
x86 Family 15 Model 2 Stepping 9, GenuineIntel
Microcode signature: 0000002E
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 - Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX - Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB - Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 - Supports Streaming SIMD Extensions 3
SSSE3 - Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 - Supports Streaming SIMD Extensions 4.1
SSE4.2 - Supports Streaming SIMD Extensions 4.2
AES - Supports AES extensions
AVX - Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE - Supports XSAVE/XRSTOR instructions
OSXSAVE - Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 - Supports CMPXCHG16B instruction
BMI1 - Supports bit manipulation extensions 1
BMI2 - Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR - Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ - Supports PCLMULDQ instruction
POPCNT - Supports POPCNT instruction
LZCNT - Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF - Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM - Supports Performance Capabilities MSR
RDTSCP - Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT - TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST - Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 - Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID * L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW - Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 00000002 (Basic), 80000004 (Extended).
Logical to Physical Processor Map:
** Physical Processor 0 (Hyperthreaded)
Logical Processor to Socket Map:
** Socket 0
Logical Processor to NUMA Node Map:
** NUMA Node 0
No NUMA nodes.
Logical Processor to Cache Map:
Logical Processor to Group Map:
** Group 0
RANA AZEEM.Hi,
Please refer to the thread below:
Windows 8 processor requirements
https://social.technet.microsoft.com/Forums/en-US/c7ae3852-d2d4-42f7-8cae-919516d0e11d/windows-8-processor-requirements?forum=w8itprogeneral
Quote:
The raw CPU power (GHz) isn't the most important part.
If you want to run Windows 8 on your PC, here's what it takes:
Processor: 1 gigahertz (GHz) or faster with support for PAE, NX, and SSE2 (...)
RAM: 1 gigabyte (GB) (32-bit) or 2 GB (64-bit)
Hard disk space: 16 GB (32-bit) or 20 GB (64-bit)
Graphics card: MicrosoftDirectX 9 graphics device with WDDM driver
(http://windows.microsoft.com/en-US/windows-8/system-requirements)
Important are the NX bit (No eXecute) which is a security feature to disallow the execution of certain software commands (PAE, a memory address extension, is normally included in NX capable CPU's) and SSE2. SSE2 is a subset of graphical instructions
needed for the Windows 8 display. All newer AMD and Intel processors with AMD64 or Intel64 capability should show those characteristics.
We
are trying to better understand customer views on social support experience, so your participation in this
interview project would be greatly appreciated if you have time.
Thanks for helping make community forums a great place. -
Hyper-V platform remains greyed out in control panel
It appears I meet the pre-reqs but when I go to enable Hyper-V via the control panel the Hyper-V platform option is greyed out.
I have Windows 8 Pro 64-bit and run both coreinfo and the AMD tool (amdvhyperv) which suggest I'm set to go.
Not sure what else to check.
AMD Phenom(tm) 8450 Triple-Core Processor
AMD64 Family 16 Model 2 Stepping 3, AuthenticAMD
HYPERVISOR - Hypervisor is present
SVM * Supports AMD hardware-assisted virtualization
NP * Supports AMD nested page tables (SLAT)
AMD Phenom(tm) 8450 Triple-Core Processor
AMD64 Family 16 Model 2 Stepping 3, AuthenticAMD
HTT * Multicore
HYPERVISOR - Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM * Supports AMD hardware-assisted virtualization
EM64T * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX * Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS - Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT * Implements AMD MMX extensions
3DNOW * Supports 3DNow! instructions
3DNOWEXT * Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 - Supports Supplemental SIMD Extensions 3
SSE4.1 - Supports Streaming SIMD Extensions 4.1
SSE4.2 - Supports Streaming SIMD Extensions 4.2
AES - Supports AES extensions
AVX - Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE - Supports XSAVE/XRSTOR instructions
OSXSAVE - Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR * Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
PCLULDQ - Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS - Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
PDCM - Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR - Supports disabling task priority messages
EIST - Supports Enhanced Intel Speedstep
ACPI - Implements MSR for power management
TM - Implements thermal monitor circuitry
TM2 - Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE - Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Logical to Physical Processor Map:
*-- Physical Processor 0
-*- Physical Processor 1
--* Physical Processor 2
Logical Processor to Socket Map:
*** Socket 0
Logical Processor to NUMA Node Map:
*** NUMA Node 0
Logical Processor to Cache Map:
*-- Data Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64
*-- Instruction Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64
*-- Unified Cache 0, Level 2, 512 KB, Assoc 16, LineSize 64
*** Unified Cache 1, Level 3, 2 MB, Assoc 1, LineSize 64
-*- Data Cache 1, Level 1, 64 KB, Assoc 2, LineSize 64
-*- Instruction Cache 1, Level 1, 64 KB, Assoc 2, LineSize 64
-*- Unified Cache 2, Level 2, 512 KB, Assoc 16, LineSize 64
--* Data Cache 2, Level 1, 64 KB, Assoc 2, LineSize 64
--* Instruction Cache 2, Level 1, 64 KB, Assoc 2, LineSize 64
--* Unified Cache 3, Level 2, 512 KB, Assoc 16, LineSize 64Still no joy. BIOS says it's enabled, SystemInfo says it's not.
CoreInfo.exe says this:
Coreinfo v3.2 - Dump information on system CPU and memory topology
Copyright (C) 2008-2012 Mark Russinovich
Sysinternals - www.sysinternals.com
Intel(R) Core(TM) i7-3537U CPU @ 2.00GHz
Intel64 Family 6 Model 58 Stepping 9, GenuineIntel
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX * Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
EM64T * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX * Supports no-execute page protection
SMEP * Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB - Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE * Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES * Supports AES extensions
AVX * Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND * Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 - Supports bit manipulation extensions 1
BMI2 - Supports bit maniuplation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C * Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB * Supports Enhanced REP MOVSB/STOSB
PCLULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL * Supports Debug Store feature with CPL
PCID * Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM * Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE * Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST * Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC * Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Logical to Physical Processor Map:
**-- Physical Processor 0 (Hyperthreaded)
--** Physical Processor 1 (Hyperthreaded)
Logical Processor to Socket Map:
**** Socket 0
Logical Processor to NUMA Node Map:
**** NUMA Node 0
Logical Processor to Cache Map:
**-- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**-- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**-- Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
**** Unified Cache 1, Level 3, 4 MB, Assoc 16, LineSize 64
--** Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--** Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--** Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
Logical Processor to Group Map:
**** Group 0
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