Is there any way to speed up the chipscope?

Question

Hello
I have made a design to test an ADC. The timing report shows that it can runs at 200MHz. But after I added a chipscope part, the frequency became much lower.
Reduce the width and deepth of the chipscope would make it run faster, but I still want to know if there is any way else to make it faster.
Thanks for your help
Wan

Answer 1


The negative slack is in ila:
From:
U_ila/inst/ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3]/C
To: U_ila/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[226].ram.r/
I'm using 156MHz clock to ila.
  U_vio: cse_vio
  PORT MAP (
        CLK         => s_clk156_out,
        PROBE_OUT0  => vio_async_out,
        PROBE_IN0   => r_vio_async_in
  U_ila: cse_ila
  PORT MAP (
        CLK          => s_clk156_out,
        TRIG_IN      => r_ila_trig_in,
        TRIG_IN_ACK  => o_ila_trig_in_ack,
        TRIG_OUT     => o_ila_trig_out,
        TRIG_OUT_ACK => r_ila_trig_out_ack,
        PROBE0       => r_ila_data
  vio_async_in          <= "0000"  & s_trig3 & s_trig2 & s_trig1 & s_trig0;
  s_tp_mux_sel          <= vio_async_out(1 DOWNTO 0);
  s_trig_mux_sel        <= vio_async_out(3 DOWNTO 2);
  ila_data              <= s_tp0   WHEN (r_tp_mux_sel   = "00") ELSE
                           s_tp1   WHEN (r_tp_mux_sel   = "01") ELSE
                           s_tp2   WHEN (r_tp_mux_sel   = "10") ELSE
                           s_tp3   WHEN (r_tp_mux_sel   = "11") ELSE s_tp0;
  i_ila_trig_in         <= s_trig0 WHEN (r_trig_mux_sel = "00") ELSE
                           s_trig1 WHEN (r_trig_mux_sel = "01") ELSE
                           s_trig2 WHEN (r_trig_mux_sel = "10") ELSE
                           s_trig3 WHEN (r_trig_mux_sel = "11") ELSE s_trig0;
  i_ila_trig_out_ack    <= s_trig0 WHEN (r_trig_mux_sel = "00") ELSE
                           s_trig1 WHEN (r_trig_mux_sel = "01") ELSE
                           s_trig2 WHEN (r_trig_mux_sel = "10") ELSE
                           s_trig3 WHEN (r_trig_mux_sel = "11") ELSE s_trig0;
  process(s_clk156_out)
  begin
   if(rising_edge(s_clk156_out)) then
    r_vio_async_in0     <= vio_async_in;
    r_vio_async_in      <= r_vio_async_in0;
    r_ila_trig_in0      <= i_ila_trig_in;
    r_ila_trig_in       <= r_ila_trig_in0;
    r_ila_trig_out_ack0 <= i_ila_trig_out_ack;
    r_ila_trig_out_ack  <= r_ila_trig_out_ack0;
    r_tp_mux_sel0       <= s_tp_mux_sel;
    r_tp_mux_sel        <= r_tp_mux_sel0;
    r_trig_mux_sel0     <= s_trig_mux_sel;
    r_trig_mux_sel      <= r_trig_mux_sel0;
    r_ila_data0  <= ila_data;
    r_ila_data   <= r_ila_data0;
   end if;
  end process;
Thanks, Wen