Issue in Post Route Simulation related with critical path

Question

I am using ISE14.4. I got critical path value 1.704 ns for my system. In post route simulation I gave clock period 1.705 ns, It should work as clock period is greater than critical path but in post route simulation I am getting this warning in ISIM
at 104057 ps, Instance /test/uut/count_0/ : Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK; Expected := 0.19 ns; Observed := 0.174 ns; At : 104.002 ns.
 I checked my system is working without this warning at 2.37 ns clock period. Any time period less than this value gives "XX" output.
Is my understanding is right?  

Answer 1

Is this an internal path ie from a register to register within the uut or is it from testbench to uut. If latter, make sure you are giving the data correctly. If former, this shows that xilinx timing results are not accurate which is unlikely.
Also your 1.705 is a setup timing result but the timing violation is a hold violation. Hold violations don't get resolved by increasing the clock period. So this path is probably a external path (which may include synchronization). Take a timing report of this specific path and post here.