Post layout simulation in ModelSim

Hi,
I have written a code in VHDL and synthesised in Virtex-5 LX155 without errors. I have verified behavioural simulation using ModelSim DE 10.2c . I want to do Post-route simulation in ModelSim. I have compiled the libraries SIMPRIMS successfully. When trying to simulate, I get a lot of errors stating " Instantiation of X_LUT6MUX64 failed. The design unit was not found" ,
" Instantiation of X_LUT5MUX32 failed. The design unit was not found." . I tried compling the libraries many times but no use.
Pls help.
Deepa.

Hi,
Make sure you are compiling library properly.
Can you try simulating any Xilinx example design to check if the same issue exist?
Thanks,
Anusheel
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Similar Messages

Issue in Post Route Simulation related with critical path

I am using ISE14.4. I got critical path value 1.704 ns for my system. In post route simulation I gave clock period 1.705 ns, It should work as clock period is greater than critical path but in post route simulation I am getting this warning in ISIM
at 104057 ps, Instance /test/uut/count_0/ : Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK; Expected := 0.19 ns; Observed := 0.174 ns; At : 104.002 ns.
I checked my system is working without this warning at 2.37 ns clock period. Any time period less than this value gives "XX" output.
Is my understanding is right?

Is this an internal path ie from a register to register within the uut or is it from testbench to uut. If latter, make sure you are giving the data correctly. If former, this shows that xilinx timing results are not accurate which is unlikely.
Also your 1.705 is a setup timing result but the timing violation is a hold violation. Hold violations don't get resolved by increasing the clock period. So this path is probably a external path (which may include synchronization). Take a timing report of this specific path and post here.

Post implementation simulation taking long time

http://forums.xilinx.com/t5/Simulation-and-Verification/2014-4-1-stuck-at-Executing-elaborate-step/td-p/638623
Actually i referred this link since my post implementation simulation takes a long time. i tried the verbose mode
WARNING: [VRFC 10-969] keyword 'unsigned' is not allowed here in this mode of verilog . this warning constantly gets didplayed is there some problem with this.
The simulation gets stuck at executing elaborate step...
How to turn off multithreading if that can be a problem as mentioned in the above thread.

Are you using $unsigned in your code? What I know is that if you don't use a negative symbol in Verilog then it is treated as unsigned. Can you check that and may be try to remove any unsigned keywords used in your code and see if that helps. Also a log of compile & elaboration would help refer: sim_1/behav
But if you can post your project archive then that would be the fastest means to check the issue and comment. We would like to fix the issue if its really a bug :)

XST Post-synthesis simulation differences between Virtex4 and Virtex6

Hi
I've been looking at a problem we've been having in one of our components where a register interface that we have implemented doesn't seem to be behaving correctly. We've used ISE 14.1 and 14.6, and simulated in ISim and ModelSim 6.6d, which both display the weird behavior. I've attached the project, source, simulation and post-synthesis code which display the issue.
We write a value (0x3FFF) to a register (in the case of the simulation 0xC) When that register is read back, we would expect 0x3FFF on reg_response_rdata. Indeed with pre-synthesis simulation, and post-synthesis on Virtex4, this is what we find. However on Virtex6 the response is 0x8000. Through trial and error we can fix this by changing line 98 of the source to the commented out line 99. Note that the implementation of pad_reg and pad_vector are identical, save for pad_vector taking the length as an argument.
To recreate run ab_dc.do in your favourite simulator. This simulates a register write to pre and post synthesis models. Notice the reads return different results depending on which hardware has been synthesised, and depending on whether pad_reg or pad_vector are used. Note also that the change to fix the behavior on line 98/99 isn't the same register that we try to write to/read from.
When it is broken (ie using pad_reg) we get the following warning: WARNING:Xst:2999 - Signal 'debug_counter', unconnected in block 'ab_dc_pre_comp', is tied to its initial value. I'm not sure what the initial value of debug counter can/should be. This warning doesn't appear when using pad_vector.
Files in zip:
./ab_dc.vhd                                                                                The source
./WarningOutput.txt                                                                   A comparision of the warnings from ISE14.1 when compiling for Virtex6. Broken = pad_reg, Fixed = pad_vector
./xilinxTest.ise                                                                           The ISE project file
./netgen/synthesis/v4_ab_dc_comp_synthesis.vhd                  ab_dc.vhd synthesised for Virtex4 using ISE14.1 using pad_reg
./netgen/synthesis/v6_ab_dc_comp_synthesis.vhd                  ab_dc.vhd synthesised for Virtex6 using ISE14.1 using pad_reg
./netgen/synthesis/v6_fix_ab_dc_comp_synthesis.vhd            ab_dc.vhd synthesised for Virtex6 using ISE14.1 using pad_vector
./sim/ab_dc.do                                                                           TCL to compile and run simulation
./sim/ab_dc_tb.vhd                                                                    Simulation to write to register 0xC and then read from it.
./sim/wave.do                                                                            Useful signals to recreate problem
This looks to me like a bug in XST. I'm happy to be proven wrong though!
Thanks

Looks like a parser issue to me, in case of V4 device XST uses an old parser and for V6 devices XST uses new parser. Check below AR:
http://www.xilinx.com/support/answers/32927.html
Thanks,
Anusheel
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.
Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
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Blog Post Layout issue

I am creating a blog for a new website. I am currently using the default layouts. When I add a post as a test it shows up perfectly when I use the preview mode. When I check it via the website the blog post list is fine but when you open the blog post page it just the text etc with no CSS. What would be causing this? Is this something I have inadvertently done or is a system issue. I have not had this problem before with BC Blogs. As far as I can see the relevant CSS links etc are on the page.
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Hi Cordie,
Sounds like there's no template assigne to the blog. Make sure you check that http://alexpavelescu.worldsecuresystems.com/Jing/2013-05-29_1520.png
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Poster layout and tiffs

Hi
I would like to create a large poster roughly 4ft square made up of tif images (22 of them). I've tried using powerpoint or keynote and they are both very slow.
I am wondering if there is an alternative software (under $100) that would work better for this....eg, how is The Print Shop?
or do I need more ram or something?
Currently running an imac (intel core duo) with 1GB ram in 1 memory slot. Will take up to 2GB total. Will the extra gig make a big difference? Or is the software the limitation?
Any advice appreciated
Cheers
Tracy

I posted this to you other thread. I think it may help you out.
Tracy:
We all agree; more RAM is better. Also, I would recommend an external hard drive to work off of. External FireWire 400 drives can be had for around $120.00 (USD). When it comes to graphic design software, there are plenty of retail packages to choose from. However, you are not limited to pay-to-use solutions. There are dozens of FREE Open Source packages to choose from. 2 of my favorites are, GIMP.app (nearly a clone of PhotoShop), InkScape (like Illustrator) and Scribus, a desktop publishing program similar to Quark or Adobe PageMaker. You can get them here: http://www.opensourcemac.org/
If I were designing a large poster I would use an app like Illustrator or Quark to create my page layout.
Tip: Reset your font cache. This will assist design programs in opening and responding faster.
Hope this helps.

How to create Inventory Posting layout

how to layout report to display
Item,Total quantity of item delivered,returned
thanks

Hi Romel,
Please check below link.
Sample layouts and reports - Business One - SCN Wiki
http://www.pioneerb1.com/wp-content/uploads/2012/04/How-to-work-with-Crystal-Reports-8.8.pdf
SAP Business One Crystal Enhancements and Integration - YouTube
Hope this helps
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Atul Chakraborty

Quickie Benchmark: Modelsim vs. Vivado Simulator

Guys,
In the hopes of finding a faster simulator I ran an unscientific benchmark on a portion of my design.
I ran for 100,000 clock cycles which is enough to get a few hundred result samples. Both simulators were run in interactive mode with the wave window open. Both simulators were run in their standard configuration without optimizations for speed. My design is FFT core heavy. Input and output is by textio.
Run Times:
Vivado Simulator = 3 minutes 0 seconds.
Modelsim = 4 minutes 40 seconds
Load times (startup) were about the same for both simulators.
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I have some more info on the long simulation time for FFT heavy simulations.
Early in the development process I wanted to be able to display memory contents while debugging. By default Vivado Simulator does not provide visibility into memories. You have to set a property in order to make memory contents visible.
set_property -name {xsim.elaborate.debug_level} -value {all} -objects [current_fileset -simset]
I suspected that turning on this property was slowing down my simulation so I ran the same simulation with it enabled and with it commented out.
Simulation time in my small experiment was reduced from 40 seconds to 8 seconds by commenting out this tcl command, a factor of 5 improvement. I don't know if this improvement scales to long simulations but I suspect so.
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Reg : Simulation in FB01

Hi,
We have Custom program to post the document in FB01 using BDC.User asked us to show the data in ALV before posting the document like simulation in FB01. We have documents in the internal table before passing the data into BDC program.?
Is it possible to simulate the document like in FB01 Simulation.? Is it there any function module to simulate the FI doucuments.?
Thanks in Adavance
P.Senthil Kumar

Hi Thomas,
Is this function module(BAPI_ACC_DOCUMENT_CHECK) act like simulation in FB01.My requirement is that in selection screen, i want to add "Test Run Only" option,If user selected this one then i want to show the required details for posting and simulation of posting data but actual posting should not happen when i executing this program with test run.
Actually this custom program already created by some one which has BDC program to post the document.so i need to add one option test run.
Layout should be display the following fields (Layout data should have both credit and debit entries)
Documnet Number   (test Run)
Reference             BKPF-XBLNR
Company Code     BSEG-BUKRS
Item             BSEG-BUZEI
Currency             BKPF-WAERS
Posting key             BSEG-BSCHL
Account             BSEG-HKONT
Amount              BSEG-WRBTR
Material             BSEG-MATNR
Quantity             BSEG-MENGE
Trading Partner     BSEG-VBUND
Cost Centre             BSEG-KOSTL
Profit Center            BSEG-PRCTR
Functional Area   BSEG-FKBER
Sales order         BSEG-VBEL2
Regards
P.Senthil Kumar
Edited by: senthil kumar on Mar 11, 2010 12:02 PM
Edited by: senthil kumar on Mar 11, 2010 12:03 PM
Edited by: senthil kumar on Mar 11, 2010 2:19 PM

Exit Function ZUPF_EXCEL* in Web Layout

Hi gurus,
I created an Exit Function based in Standard function "UPF_EXCEL_AFTER_DATA_PUT_01". I put this function in the field 'name of writing module' like explains very good Alberto Sabate in his post (layout in change mode). The functions runs very well in GUI. The problem occurs when I tried to do the same in a Web layout. The function it doesn't works.
I would like to know if this kind of functions it doesn't works in Web or it is a problem of our code or a need a modification in WIB ?.
Another question, it's posible to change the protection of a cell (lock a cell) with this function ? OR this is only posible with a VB Macro ?
Thanks in advanced.
Carlos.

Hi Marc,
Thank You very much for your reply, but now We have a problem ))
I explain our problem ...
We have to control the value of a header characteristic in a layout to fill a table, we have a Hierarchy Variable to control the layout, and this one shows characteristics combinations from Transaction Data. When we navigate ( select another combination) with this header char we have to control the changes of it. All in Web format.
We try with a Standar Exit Function, but in the internal Table XTH_DATA we don't know which is the value of the chararacteristic that layouts shows.
Do you know if there is another exit function that is executed in Web layout with this functionality ?.
Thanks in advanced and Best Regards,
Carlos.

What are Validation and simulator

can any one explain what are Validation and Simulators are ???
what is there importance and how they work in SAP ??
Regards,
Milindkumar

Are you referring to validation rules and simulations? Whereby validations allow the checking of values and combinations of data as they are being entered in SAP. Because the data is validated before it is posted, only correct information enters the system. For example if you have a cost center X that should not post to account Y. You create a validation that checks to see if cost center X is entered whether the account is Y. If the account is Y the validation will stop the entry from being made.
Simulations normally are when data is checked for accuracy or verfied before posting. Simulations usually allow the verification of data by displaying that entries that will post or will be created only after the post button or process occurs.

How is the posting key determined?

Hi,
I have a general question about posting keys.
What is the logic behind the posting keys (customizing OB41)?
I think we have 2 possibilities:
With automatic postings, the posting keys are picked up from the "Account assignment" in Customizing (OMWB).
With manual postings, the posting key is selected manually when making the posting.
Do you have any more information about it?
Thank you for your feedback.
Kind regards,
Linda

Linda,
Posting Key is a 2 character numerical key that controls the entry of line items.
The posting key determines:
Account type
Debit/credit posting
Layout of entry screens
When you enter a posting, you enter a posting key for each item. This key determines how the item is posted. Posting keys are defined at client level and therefore apply to all company codes.
The posting key determines:
The data you can enter in the line item
How data you post is processed
How the system updates the data you enter
Posting keys are differentiated by customer, vendor and G/L accounts. Apart from the General Ledger Accounting (FI-GL) and Accounts Receivable and Payable (FI-AR/AP) components, there are also posting keys for asset and material accounts.
Hope that helps.
Nandita

Re run simulation

Hi,
We have to re run the simulation after adding some signals to the waveform window to see thier graphs. Since it takes a long time for post synthesis and post implementation simulations is there a alternative to this?

Hi,
One option is to create the dump for all the signals & later add whatever signal you want to see. This option will create huge dump files.
Example:
open_vcd xsim_dump.vcd
log_vcd /tb/dut/*
run all
close_vcd
quit
Refer to page 90 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug900-vivado-logic-simulation.pdf for details.

FSG vs posting Key

Hi experts
The Field status group populated in the G/L master helps during the posting of transactions for deciding the status of the field i.e suppressed,required and optional.
And the posting key also does the same functio.
Then my question is why is why SAP has provided both the tools.
Answer will be rewarded with points.
Thanks in advance
Surendra

Hi
This is used to define which fields are displayed when you post accounting transactions to a G/L account. A field may have one of the following statuses:
hidden (suppressed)
Entry required (required field)
Ready for input (optional field)
Display Field
The field status is defined outside the master record. The field status of each field is defined under a field status group, which is then assigned to a GL Master record. Field status groups are independent of the company code and are grouped under field status variant.
Two-character numerical key that controls the entry of line items. The posting key determines:
Account type
Debit/credit posting
Layout of entry screens
When you enter a posting, enter a posting key for each item. This key determines how the item is posted. Posting keys are defined at client level and therefore apply to all company codes. The posting key determines:
The data you can enter in the line item
How data you post is processed
How the system updates the data you enter
The document type specifies which account types you can post to. The posting key specifies which account types you can post to. A posting key can only be entered for an account type which is permitted for that document type
Thus field status is used for the entry at the field level whereas the posting key determines as to how SAP treats the entry at the line item level.
Pls assign points if the information is useful to you.
Regards
Sanil Bhandari

T.code MIR6: before posting an invoice, could I simulate document posting?

Hi All,
with reference to t.code MIR6, I wonder if SAP allow me to simulate the document before posting it?
I can't see the button ...
Thanks
Gandalf

MIR7 is for parking of invoicing you can aslo simulate here and MIRO is used for posting and simulation both. If you have parked your invoices then you can check through MIR6 through MIR6 you can go to post you parked documents by clickng on pencil button (edit).
If it helps, kindly give points.
Regards,
RM

Post layout simulation in ModelSim

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