[Kernel module development ]Makefile issue with .cpp

Question

Hi all,
I'm currently in the process of rewriting an external kernel module, that shares a big part of its code with the Windows version of the driver.  The common files are C-code, but for some Windows-related obscure reason their extension is .cpp.  In the previous version of the driver, we had to run a small script on the files to convert the .cpp to .c files for the linux driver.  Not very elegant.  So I'd like to be able to work directly on the .cpp files, but compile them as "pure C" files.  This would allow us to directly work on the files fetched from the VCS, and it's a lot nicer!
Unfortunately, when compiling a kernel module, it's ultimately the kernel's Makefile that's called to actually do the compilation, and no rule is defined in it to handle .cpp files, even when they contain pure-C code.  So my source files are never found, and I get a nice "no rule to make target".
Would any of you know a way to do this?  I know of the "-x c" gcc option, but as I don't really master Makefiles, I don't know if I can pass it to the kernel Makefile, and no more how...  I looked all over the internet (took me a long time to read all of it...) and found nothing so far.
Thanks a lot

Answer 1

It's a bash check ([), it tells the script to add a conditional makedepends (if the kernel has that name, add that package as a dependency to build). It's optional, so it doesn't do any harm.
Thanks for looking though .