MIG DDR3 on Virtex-6 - Unroutable situation in PaR

Question

Hello,
I have a SP6 design with MIG and at P&R I get this warning:
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
Unroutable signal: u_ddr3_controller/memc1_wrapper_inst/memc1_mcb_raw_wrapper_inst/ioi_drp_clk_c pin:
u_ddr3_controller/memc1_wrapper_inst/memc1_mcb_raw_wrapper_inst/ioi_drp_clk_derived_clock_cb/I0
This results in one signal not routed. There were some necessary tweaks in the default generated files to configure the correct clocking, and since this is within those files, are there any other changes necessary to get P&R running without this issue?
Thanks in advance.

Answer 1

Thanks guys.
From FPGA editor i can in fact see that the problem is in the calibration clock. ioi_drp_clk is not somehow connected to the BUFG. But i don't understand why. I checked vsrunga's tip and i'm setting the calibration clock at 66MHz. So it should be good.
Firstly I was using a 25MHz source clock, but now I managed to get a low-jitter external clock synthesizer to get me 166.66MHz. So my clocking configuration for the MIG is:
C1_CLKOUT0_DIVIDE : integer := 1;  -- 666MHz sysclk_2x
C1_CLKOUT1_DIVIDE : integer := 1;  -- 666MHz sysclk_2x_180
C1_CLKOUT2_DIVIDE : integer := 4;  -- 166MHz user fabric
C1_CLKOUT3_DIVIDE : integer := 10; -- 66.6MHz calibration clock
C1_CLKFBOUT_MULT : integer := 4;  -- Generate 666MHz from 166
C1_DIVCLK_DIVIDE : integer := 1;
I guess that this is correct (tell me if not), so i don't see why P&R is having trouble.
[NOTE] Device is a Spartan-6, not a Virtex-6 as wrongly mentioned in the topic.
PCF and NCD files attached as requested by vemulad.
Thanks.