Axi Master DDR (MIG) tester

Hi guys I'm trying to create a DDR stresser on my project, so I created an Vivado HLS IP core that has one axi-master interface and one axi-lite-slave(for parameters) the code is bellow
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
unsigned int memDDR3Tester(unsigned int start, unsigned int size, unsigned int mode, unsigned int data, volatile unsigned int *memPtr, unsigned int *expectedVal, unsigned int *failedAddr, unsigned int *numErrors)
#pragma HLS INTERFACE s_axilite port=numErrors bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=failedAddr bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=expectedVal bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=start bundle=CRTL_BUS
#pragma HLS INTERFACE m_axi depth=512 port=memPtr
#pragma HLS INTERFACE s_axilite port=data bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=mode bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=size bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS
unsigned int result = 0;
unsigned int idxMemAddr = 0;
unsigned int errorCounter = 0;
*numErrors = 0;
*expectedVal = 0;
*failedAddr = 0;
switch (mode)
* Send 0xAA55 (16b1010101001010101) or 0x55AA if the address is odd/even
* write then read and stop on the first error
case 0:
// Write
for (idxMemAddr = 0; idxMemAddr < size; idxMemAddr++)
unsigned char isOdd = (idxMemAddr % 2);
unsigned int value = (isOdd)?0x55AA:0xAA55;
memPtr[idxMemAddr] = value;
// Read
for (idxMemAddr = 0; idxMemAddr < size; idxMemAddr++)
unsigned char isOdd = (idxMemAddr % 2);
unsigned int value = (isOdd)?0x55AA:0xAA55;
if (memPtr[idxMemAddr] != value)
result = 1;
*expectedVal = value;
*failedAddr = idxMemAddr;
// Bail out on the first error
*numErrors = 1;
break;
break;
* Send an incremental value but don't stop if some error occured and return the number of errors
case 1:
// Write
for (idxMemAddr = 0; idxMemAddr < size; idxMemAddr++)
unsigned int value = idxMemAddr;
memPtr[idxMemAddr] = value;
// Read
for (idxMemAddr = 0; idxMemAddr < size; idxMemAddr++)
unsigned int value = idxMemAddr;
if (memPtr[idxMemAddr] != value)
result = 1;
errorCounter++;
*numErrors = errorCounter;
break;
* Send just a value and read it back
case 2:
memPtr[start] = data;
if (memPtr[start] != data)
result = 1;
*expectedVal = data;
*failedAddr = start;
break;
* Send on mode burst (memset) the value 0xAA55 (16b1010101001010101)
case 3:
//memset((unsigned int*)memPtr,(int)0xAA55,(size_t)(sizeof(unsigned int)*size));
// Write
for (idxMemAddr = 0; idxMemAddr < size; idxMemAddr++)
memPtr[idxMemAddr] = 0xAA55;
// Read
for (idxMemAddr = 0; idxMemAddr < size; idxMemAddr++)
if (memPtr[idxMemAddr] != 0xAA55)
result = 1;
errorCounter++;
*numErrors = errorCounter;
break;
return result;
#include <stdio.h>
unsigned int memDDR3Tester(unsigned start, unsigned int size, unsigned int mode, unsigned int data, volatile unsigned int memPtr[512000000], unsigned int *expectedVal, unsigned int *failedAddr, unsigned int *numErrors);
int main()
unsigned int memPtr[10];
unsigned int expectedVal;
unsigned int failedAddr;
unsigned int numErrors;
unsigned int result;
printf("Test mode 0\n");
result = memDDR3Tester(0,10,0,0,memPtr,&expectedVal,&failedAddr,&numErrors);
printf("Result mode 0: %d Expected: %d failedAddr:%d numErrors:%d\n",result,expectedVal,failedAddr,numErrors);
for (int idx = 0; idx < 10; idx++)
printf("DDR3[%d]=%x\n",idx,memPtr[idx]);
return 0;
The first problem is that I can simulate the on C/C++ but not co-simulate I get those errors:
Determining compilation order of HDL files.
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/laraujo/memDDR3Tester/solution1/sim/verilog/AESL_axi_master_memPtr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_memPtr
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/laraujo/memDDR3Tester/solution1/sim/verilog/AESL_axi_slave_CRTL_BUS.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_slave_CRTL_BUS
ERROR: [VRFC 10-46] write_start_count is already declared [C:/Users/laraujo/memDDR3Tester/solution1/sim/verilog/AESL_axi_slave_CRTL_BUS.v:201]
ERROR: [VRFC 10-46] write_start_run_flag is already declared [C:/Users/laraujo/memDDR3Tester/solution1/sim/verilog/AESL_axi_slave_CRTL_BUS.v:202]
ERROR: [VRFC 10-46] write_start is already declared [C:/Users/laraujo/memDDR3Tester/solution1/sim/verilog/AESL_axi_slave_CRTL_BUS.v:738]
ERROR: [VRFC 10-552] declarations not allowed in unnamed block [C:/Users/laraujo/memDDR3Tester/solution1/sim/verilog/AESL_axi_slave_CRTL_BUS.v:738]
ERROR: [VRFC 10-1040] module AESL_axi_slave_CRTL_BUS ignored due to previous errors [C:/Users/laraujo/memDDR3Tester/solution1/sim/verilog/AESL_axi_slave_CRTL_BUS.v:11]
ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/memDDR3Tester/xsimk.exe" does not exist
These are the results for C/C++ simulation:
Compiling ../../../test_core.cpp in debug mode
Generating csim.exe
Test mode 0
Result mode 0: 0 Expected: 0 failedAddr:0 numErrors:0
DDR3[0]=aa55
DDR3[1]=55aa
DDR3[2]=aa55
DDR3[3]=55aa
DDR3[4]=aa55
DDR3[5]=55aa
DDR3[6]=aa55
DDR3[7]=55aa
DDR3[8]=aa55
DDR3[9]=55aa
@I [SIM-1] CSim done with 0 errors.
Anyway after exporting to vivado and connecting the mig and the microblaze through an Axi Interconnect, I got this: (Artix 7 Avnet demoboard)
The addresses:
On Xilinx SDK my code to initialize the core and test it this:
#include <stdio.h>
#include <xmemddr3tester.h>
#include <xparameters.h>
#include <xil_cache.h>
XMemddr3tester doMemDDR3Test;
XMemddr3tester_Config *doMemDDR3Test_cfg;
#define SIZE_ARRAY 10
unsigned int *topMemDDR = (unsigned int *)0x80000000;
void initDDRTester()
int status = 0;
doMemDDR3Test_cfg = XMemddr3tester_LookupConfig(XPAR_MEMDDR3TESTER_0_DEVICE_ID);
if (doMemDDR3Test_cfg)
status = XMemddr3tester_CfgInitialize(&doMemDDR3Test,doMemDDR3Test_cfg);
if (status != XST_SUCCESS)
printf("Failed to inititalize\n");
int main()
int idx = 0;
unsigned int error;
initDDRTester();
for (idx = 0; idx < SIZE_ARRAY; idx++)
topMemDDR[idx] = idx*2;
printf("DDR3 tester console\n");
Xil_DCacheFlushRange((unsigned int)topMemDDR,sizeof(unsigned int)*SIZE_ARRAY);
XMemddr3tester_Set_mode(&doMemDDR3Test,0);
XMemddr3tester_Set_data(&doMemDDR3Test,0);
XMemddr3tester_Set_start(&doMemDDR3Test,0x80000000);
XMemddr3tester_Set_size(&doMemDDR3Test,(unsigned int)SIZE_ARRAY);
XMemddr3tester_Start(&doMemDDR3Test);
while (!XMemddr3tester_IsDone(&doMemDDR3Test));
error = XMemddr3tester_Get_return(&doMemDDR3Test);
printf("Test done %d\n",error);
Xil_DCacheInvalidateRange((unsigned int)topMemDDR,sizeof(unsigned int)*SIZE_ARRAY);
for (idx = 0; idx < SIZE_ARRAY; idx++)
printf("DDR3[%d]=%x\n",idx,topMemDDR[idx]);
return 0;
By some reason it seems that is the data is not been sent to the MIG (I though initialiy that could be a problem with the Cache but it seems that is not the case, anyway I disabled the cache on the microblaze)
So to resume the questions:
1) Someone knows what could be wrong on the Co-Simulation
2) The address autogenerated for the mig is also updated somehow on the HLS core? (I tried to manually set the pointer address on Vivado HLS but it didn't synthesised)
3) Do you guys seem something wrong on this design?
4) Can I use the ILA to see the DDR3 interface (Or should I use the "Mark Debug option?)
Thanks.

Hi thanks, I've changed the parameter name and the previous error on the simulation disappeared, but now I have a comsim.pc.exe crash during the C post checkign phase.
INFO: [Common 17-206] Exiting xsim at Tue Jul 14 10:48:04 2015...
@I [SIM-316] Starting C post checking ...
@E [SIM-379] Detected segmentation violation, please check C tb.
@E [SIM-362] Aborting co-simulation: C TB post check failed.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***
So what I did was to simplify the IP core more to only send 0xaa55 or 0x55aa on the master interface:
core.cpp (Used to generate the IP core)
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
// 1Gb limit
#define MAX_MEM_SIZE 200000
unsigned int memDDR3Tester(unsigned int size, volatile unsigned int *memPtr, unsigned int *expectedVal, unsigned int *failedAddr, unsigned int *numErrors)
#pragma HLS INTERFACE s_axilite port=numErrors bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=failedAddr bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=expectedVal bundle=CRTL_BUS
#pragma HLS INTERFACE m_axi depth=512 port=memPtr
#pragma HLS INTERFACE s_axilite port=size bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS
unsigned int result = 0;
unsigned int idxMemAddr = 0;
unsigned int errorCounter = 0;
*numErrors = 0;
*expectedVal = 0;
*failedAddr = 0;
* Send 0xAA55 (16b1010101001010101) or 0x55AA if the address is odd/even
* write then read and stop on the first error
// Write
for (idxMemAddr = 0; idxMemAddr < size; idxMemAddr++)
#pragma HLS LOOP_TRIPCOUNT min=256000000 max=256000000 avg=256000000
unsigned char isOdd = (idxMemAddr % 2);
unsigned int value = (isOdd)?0x55AA:0xAA55;
memPtr[idxMemAddr] = value;
/*if (idxMemAddr > size)
break;*/
// Read
for (idxMemAddr = 0; idxMemAddr < size; idxMemAddr++)
#pragma HLS LOOP_TRIPCOUNT min=256000000 max=256000000 avg=256000000
unsigned char isOdd = (idxMemAddr % 2);
unsigned int value = (isOdd)?0x55AA:0xAA55;
if (memPtr[idxMemAddr] != value)
result = 1;
*expectedVal = value;
*failedAddr = idxMemAddr;
// Bail out on the first error
*numErrors = 1;
break;
/*if (idxMemAddr > size)
break;*/
return result;
test core
#include <stdio.h>
unsigned int memDDR3Tester(unsigned int size, volatile unsigned int *memPtr, unsigned int *expectedVal, unsigned int *failedAddr, unsigned int *numErrors);
unsigned int memPtr[20];
int main()
unsigned int expectedVal;
unsigned int failedAddr;
unsigned int numErrors;
unsigned int result;
printf("Test mode 0\n");
result = memDDR3Tester(10,memPtr,&expectedVal,&failedAddr,&numErrors);
printf("Result mode 0: %d Expected: %d failedAddr:%d numErrors:%d\n",result,expectedVal,failedAddr,numErrors);
for (int idx = 0; idx < 10; idx++)
printf("DDR3[%d]=%x\n",idx,memPtr[idx]);
return 0;
But again the simulation on C/C++ works but I have some trouble on the co-simulation part.
I also tried to change the for loop to hava a fixed constant iteration and on the midle of its code break if the condition size is met:
// Write
for (idxMemAddr = 0; idxMemAddr < MAX_MEM_SIZE; idxMemAddr++)
unsigned char isOdd = (idxMemAddr % 2);
unsigned int value = (isOdd)?0x55AA:0xAA55;
memPtr[idxMemAddr] = value;
if (idxMemAddr > size)
break;
The problem is that if I try to synthesize this I got this error:
Stack dump:
0. Running pass 'Generate interface primitives' on module 'C:/Users/laraujo/ddrStresserVIV_2015/solution1/.autopilot/db/a.o.2.bc'.
0x000007FEC7CBE4E0 (0x0000000000000003 0x00000000059368D0 0x00000000059368D8 0x0000000002924BF0), ?save_object_ptr@?$pointer_oserializer@Vxml_oarchive@archive@boost@@VTransition@DBFsm@fsmd@@@detail@archive@boost@@EEBAXAEAVbasic_oarchive@234@PEBX@Z() + 0x331210 bytes(s)
0x000007FEC773080A (0x0000000000000004 0x0000000005553D20 0x0000000006A51FB0 0x00000000001D8200), ?main@Syn@@YAHHPEAPEAD@Z() + 0x5A1C3A bytes(s)
0x000007FEC77300D3 (0x0000000006E80350 0x00000000001D7DC0 0x0000000006A52E60 0x00000000001D81C0), ?main@Syn@@YAHHPEAPEAD@Z() + 0x5A1503 bytes(s)
0x000007FEC7732D7A (0x0000000000000000 0x0000000006E819D0 0x0000000005553D20 0x0000000006DBEDD0), ?main@Syn@@YAHHPEAPEAD@Z() + 0x5A41AA bytes(s)
0x000007FEC7731385 (0x00000000001D8300 0x00000000001D8410 0x00000000059366F0 0x00000000059366F0), ?main@Syn@@YAHHPEAPEAD@Z() + 0x5A27B5 bytes(s)
0x000007FEC7738D25 (0x0000000000000000 0x00000000059366F0 0x0000000000000000 0x0000000000000001), ?main@Syn@@YAHHPEAPEAD@Z() + 0x5AA155 bytes(s)
0x000007FEC7C56777 (0x0000000000000004 0x0000000006E04480 0x0000000005936460 0x0000000006D8EE90), ?save_object_ptr@?$pointer_oserializer@Vxml_oarchive@archive@boost@@VTransition@DBFsm@fsmd@@@detail@archive@boost@@EEBAXAEAVbasic_oarchive@234@PEBX@Z() + 0x2C94A7 bytes(s)
0x000007FEC7C557B0 (0x0000000000000004 0x00000000001D8CD9 0x0000000006D8EE90 0x0000000000000000), ?save_object_ptr@?$pointer_oserializer@Vxml_oarchive@archive@boost@@VTransition@DBFsm@fsmd@@@detail@archive@boost@@EEBAXAEAVbasic_oarchive@234@PEBX@Z() + 0x2C84E0 bytes(s)
0x000007FEC7149148 (0x00000000000011C2 0x00000000001D8CD9 0x0000000000000000 0x000007FEC827CF70)
0x000007FEEFB2B1A4 (0x000000000235DCC0 0x000000006DED2E12 0x0000000006A303B0 0x00000000002FD600), ??1TclManager@xpcl@@QEAA@XZ() + 0x1F94 bytes(s)
0x000007FEEFB2D9C9 (0x000000006DF52B18 0x0000000000000096 0x0000000006A3CA50 0x000000006DF1937C), ?setResultObj@TclCommand@xpcl@@QEAAXPEAUTcl_Obj@@@Z() + 0x49 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000096 0x0000000006A3DA50 0x0000000000000096), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE51D9E (0x00000000002FD600 0x0000000006A3CA50 0x0000000000000096 0x0000000000000096), Tcl_EvalEx() + 0x99E bytes(s)
0x000000006DE52A28 (0x0000000000000000 0x00000000023268B8 0x0000000000000001 0x0000000000000002), TclEvalObjEx() + 0x348 bytes(s)
0x000000006DE5A88A (0x0000000000000000 0x00000000002FD600 0x00000000002FD600 0x0000000000000000), TclDumpMemoryInfo() + 0x340A bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000002 0x00000000023268B8 0x00000000023268B8), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x0000000006A0BCA0 0x000000006DF53178 0x0000000000000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DE94464 (0x0000000003771A50 0x00000000002FD600 0x000000006DF53178 0x000000006DEE329B), Tcl_ExprObj() + 0x634 bytes(s)
0x000000006DE52AA6 (0x0000000000000753 0x0000000000000000 0x0000000000000003 0x0000000000000003), TclEvalObjEx() + 0x3C6 bytes(s)
0x000000006DE59F00 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x00000000002EFE60), TclDumpMemoryInfo() + 0x2A80 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000003 0x0000000002326848 0x0000000002326848), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x0000000006978220 0x000000000027BE36 0x6666666600000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DE94464 (0x0000000006A30110 0x00000000002FD600 0x0000000000000000 0x0000000000000000), Tcl_ExprObj() + 0x634 bytes(s)
0x000000006DE52AA6 (0x0000000002326800 0x00000000002FD600 0x0000000000000000 0x0000000000000002), TclEvalObjEx() + 0x3C6 bytes(s)
0x000000006DE6909A (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x00000000023267F0), TclDumpMemoryInfo() + 0x11C1A bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000002 0x00000000023267E8 0x00000000023267E8), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x0000000006A3C250 0x0000000000000000 0x0000000000000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DEDFED4 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x000000006DF193BD), TclObjInterpProcCore() + 0x74 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000004 0x00000000023265B8 0x00000000023265B8), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x0000000006A46280 0x0000000000000000 0xFFFFFFFF00000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DEDFED4 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x0000000000000000), TclObjInterpProcCore() + 0x74 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000100000005 0x0000000002326348 0x0000000002326348), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x0000000006B2E270 0x0000000000000000 0x0000000000000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DEDFED4 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x0000000000000000), TclObjInterpProcCore() + 0x74 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000001 0x00000000023261F8 0x00000000023261F8), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x0000000006A39340 0x0000000002326040 0x0000000000000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DE94464 (0x0000000006BA4660 0x00000000002FD600 0x0000000002325DA0 0x00000000001DBCA0), Tcl_ExprObj() + 0x634 bytes(s)
0x000000006DE52AA6 (0x0000000006A2AF20 0x0000000000000000 0x0000000000000003 0x0000000002325FF0), TclEvalObjEx() + 0x3C6 bytes(s)
0x000000006DE59F00 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x00000000002EFE60), TclDumpMemoryInfo() + 0x2A80 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000003 0x0000000002326040 0x0000000000000003), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE51D9E (0x00000000002FD600 0x00000000028FD7AB 0x0000000000000003 0x0000000000000003), Tcl_EvalEx() + 0x99E bytes(s)
0x000000006DED5952 (0x00000000002FD600 0x0000000000000002 0x0000000000000001 0x0000000000000000), Tcl_SubstObj() + 0x832 bytes(s)
0x000000006DE51991 (0x00000000002FD600 0x00000000028FD6D0 0x0000000000000002 0x000007FE00000002), Tcl_EvalEx() + 0x591 bytes(s)
0x000000006DE52638 (0x00000000029335F0 0x00000000029335F0 0x00000000001DC270 0x000007FEC7E5C184), Tcl_Eval() + 0x38 bytes(s)
0x000007FEC711D735 (0x0000000000000FD5 0x0000000000000FD5 0x00000000029335F0 0x0000000000000FD5)
0x000007FEEFB2B1F3 (0x0000000006CB7430 0x0000000006A4B554 0x0000000000000001 0x00000000002FD600), ??1TclManager@xpcl@@QEAA@XZ() + 0x1FE3 bytes(s)
0x000007FEEFB2D9C9 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x000000006DF193BD), ?setResultObj@TclCommand@xpcl@@QEAAXPEAUTcl_Obj@@@Z() + 0x49 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000005 0x0000000002325960 0x0000000002325960), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x00000000058C2F40 0x0000000000000000 0x0000000000000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DEDFED4 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x000000006DE93BFC), TclObjInterpProcCore() + 0x74 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000001 0x0000000002325798 0x0000000002325798), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x0000000005A24060 0x00000000023255E0 0x0000000000000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DE94464 (0x0000000006CB4370 0x00000000002FD600 0x0000000002325340 0x00000000001DD280), Tcl_ExprObj() + 0x634 bytes(s)
0x000000006DE52AA6 (0x0000000006CB5120 0x0000000000000000 0x0000000000000003 0x0000000002325590), TclEvalObjEx() + 0x3C6 bytes(s)
0x000000006DE59F00 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x00000000002EFE60), TclDumpMemoryInfo() + 0x2A80 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000003 0x00000000023255E0 0x0000000000000003), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE51D9E (0x00000000002FD600 0x000000000564D91E 0x0000000000000003 0x0000000000000003), Tcl_EvalEx() + 0x99E bytes(s)
0x000000006DED5952 (0x00000000002FD600 0x0000000000000002 0x0000000000000001 0x0000000000000000), Tcl_SubstObj() + 0x832 bytes(s)
0x000000006DE51991 (0x00000000002FD600 0x000000000564CFB0 0x0000000000000002 0x000007FE00000002), Tcl_EvalEx() + 0x591 bytes(s)
0x000000006DE52638 (0x0000000000275870 0x0000000000275870 0x00000000001DD850 0x000007FEC7E5C184), Tcl_Eval() + 0x38 bytes(s)
0x000007FEC711D735 (0x00000000000008EB 0x00000000000008EB 0x0000000000275870 0x00000000000008EB)
0x000007FEEFB2B1F3 (0x0000000000000001 0x00000000069D3448 0x0000000000000001 0x00000000002FD600), ??1TclManager@xpcl@@QEAA@XZ() + 0x1FE3 bytes(s)
0x000007FEEFB2D9C9 (0x0000000000000000 0x0000000000000001 0x00000000055CDFE0 0x000000006DF193BD), ?setResultObj@TclCommand@xpcl@@QEAAXPEAUTcl_Obj@@@Z() + 0x49 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000009 0x0000000002324ED8 0x0000000002324ED8), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x0000000005A86490 0x0000000000000000 0x0000000000000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DEDFED4 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x0000000000000000), TclObjInterpProcCore() + 0x74 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000001 0x0000000002324D48 0x0000000002324D48), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE95688 (0x00000000002FD600 0x00000000033DBBE0 0x0000000002324B90 0x0000000000000000), Tcl_ExprObj() + 0x1858 bytes(s)
0x000000006DE94464 (0x00000000055CC390 0x00000000002FD600 0x00000000023248F0 0x00000000001DE860), Tcl_ExprObj() + 0x634 bytes(s)
0x000000006DE52AA6 (0x00000000055CA650 0x0000000000000000 0x0000000000000003 0x0000000002324B40), TclEvalObjEx() + 0x3C6 bytes(s)
0x000000006DE59F00 (0x0000000000000000 0x00000000002FD600 0x0000000000000000 0x00000000002EFE60), TclDumpMemoryInfo() + 0x2A80 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000003 0x0000000002324B90 0x0000000000000003), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE51D9E (0x00000000002FD600 0x00000000033CBBD1 0x0000000000000003 0x0000000000000003), Tcl_EvalEx() + 0x99E bytes(s)
0x000000006DED5952 (0x00000000002FD600 0x0000000000000002 0x0000000000000001 0x0000000000000000), Tcl_SubstObj() + 0x832 bytes(s)
0x000000006DE51991 (0x00000000002FD600 0x00000000033CBA10 0x0000000000000002 0x000007FE00000002), Tcl_EvalEx() + 0x591 bytes(s)
0x000000006DE52638 (0x0000000000275CD0 0x0000000000275CD0 0x00000000001DEE30 0x000007FEC7E5C184), Tcl_Eval() + 0x38 bytes(s)
0x000007FEC711D735 (0x00000000000008EB 0x00000000000008EB 0x0000000000275CD0 0x00000000000008EB)
0x000007FEEFB2B1F3 (0x000000000286D420 0x000000006DED2E12 0x00000000055CCE70 0x00000000002FD600), ??1TclManager@xpcl@@QEAA@XZ() + 0x1FE3 bytes(s)
0x000007FEEFB2D9C9 (0x0000000005931EF0 0x0000000000000000 0x0000000000000000 0x0000000000000002), ?setResultObj@TclCommand@xpcl@@QEAAXPEAUTcl_Obj@@@Z() + 0x49 bytes(s)
0x000000006DE50E50 (0x0000000000000000 0x0000000000000001 0x0000000002324370 0x0000000000000001), Tcl_ListMathFuncs() + 0x590 bytes(s)
0x000000006DE51D9E (0x00000000002FD600 0x00000000055978F0 0x0000000000000001 0x0000000000000001), Tcl_EvalEx() + 0x99E bytes(s)
0x000000006DEBA4F0 (0x00000000002F7FD0 0x00000000002F7FD0 0x00000000002FD600 0x0000000000000000), Tcl_FSEvalFileEx() + 0x250 bytes(s)
0x000000006DEC5B24 (0x0000000000000001 0x0000000000000008 0x0001F82056300000 0x000000000020C5A0), Tcl_Main() + 0x554 bytes(s)
0x000007FEEFB2D1F1 (0x0000000000000002 0x0000000000282B3A 0x0077005C00640065 0x000007FEF5AE43B8), ?issue@TclManager@xpcl@@QEAAHHPEAPEAD_N@Z() + 0x371 bytes(s)
0x000007FEC718FC52 (0x0000000000000000 0x01D0BE1535026984 0x0000000000000000 0x0000000000000000), ?main@Syn@@YAHHPEAPEAD@Z() + 0x1082 bytes(s)
0x000000013F0B124B (0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000)
0x00000000776C652D (0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000), BaseThreadInitThunk() + 0xD bytes(s)
0x00000000778FC521 (0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000), RtlUserThreadStart() + 0x21 bytes(s)
@E [HLS-102] Encountered an internal error;
For technical support on this issue, please visit http://www.xilinx.com/support.

Similar Messages

Debugging: Using JTAG to axi Master: Can't write to the memory

Hello,
I am trying to make a very simple design in order to write and read to the memory using JTAG to axi master IP core. I did my design based on the following quick take video:
https://www.youtube.com/watch?v=btJ5Q7psf9M
After downloading the bitstream and trying to work with the tcl, everything goes well until when I want to use the write command:
run_hw_axi [get_hw_axi_txns $wt]
I will receive the following error :
ERROR: [Xicom 50-38] xicom: AXI TRANSACTION FAILED
INFO: [Labtoolstcl 44-481] WRITE DATA is: 44444444_33333333_22222222_11111111
ERROR: [Common 17-39] 'run_hw_axi' failed due to earlier errors.
What is wrong?
Here is more detail about my design:
1. The only top module is the vhdl wrapper for the block design which has been generated by the ip integerator
2. The clock is running at 100MHz.
3. the reset is grounded to 0, i.e. I don't have external reset signal
4. I have tried different clock frequency while connecting it to the JTAG, didn't help
Thanks,
Aryan

I removed the clocking wizard ip and connected the clock directly to the design block. works perfectly now

JTAG to axi Master: Can't write to the memory

Hello,
I am trying to make a very simple design in order to write and read to the memory using JTAG to axi master IP core. I did my design based on the following quick take video:
https://www.youtube.com/watch?v=btJ5Q7psf9M
After downloading the bitstream and trying to work with the tcl, everything goes well until when I want to use the write command:
run_hw_axi [get_hw_axi_txns $wt]
I will receive the following error :
ERROR: [Xicom 50-38] xicom: AXI TRANSACTION FAILED
INFO: [Labtoolstcl 44-481] WRITE DATA is: 44444444_33333333_22222222_11111111
ERROR: [Common 17-39] 'run_hw_axi' failed due to earlier errors.
What is wrong?
Here is more detail about my design:
1. The only top module is the vhdl wrapper for the block design which has been generated by the ip integerator
2. The clock is running at 100MHz.
3. the reset is grounded to 0, i.e. I don't have external reset signal
4. I have tried different clock frequency while connecting it to the JTAG, didn't help
Thanks,
Aryan

I removed the clocking wizard ip and connected the clock directly to the design block. works perfectly now

Cannot find BT master socket to test broadband

House is less than 18months old and had all phone sockets installed prior to moving in as first occupants. BT line connected after 2weeks. Engineer did not enter house. Now have problem with broadband and have been told I need to connect the router to the BT master socket for test purposes but cannot find one! All internal sockets are standard phone sockets.
BT line comes up from ground outside on front wall near door in a BT 'Openreach' box which is a flip-down, secured by a screw. On opening this the BTincoming connection is sealed, then there is a plug, which if removed disconnects the internal lines. Then there is a connector to which the blue/white/orange leads coming out from through wall from inside the house (white covered cable) are connected. The other side of this wall is underneath the built-in kitchen units and has no master socket anywhere.
Have been banging my head trying to explain to ISP that I cannot connect to a master socket as cant find one. Should I have one or is the outside box all I get? If so, how do I connect the computer to the (6 pin) socket outside?

New build properties are now being fitted with a new Network Terminating Equipment box, the XNTE, instead of the previous NTE5 master socket. This is fitted outside the property and BT responsibility ends at the XNTE. This is the box you referred to with the flip-down cover. It contains all the master socket components. The socket in the XNTE is a BT test point and requires a special plug - it is for BT use only.
In order to eliminate your internal wiring you would need to connect a standard slave socket at the XNTE in place of the white covered cable. Make a note of the way the existing cable is connected. The official connections are pin 2 - Blue, 3 - Brown, 4 - green, 5 - Orange.
See http://www.openreach.co.uk/orpg/networkinfo/developnetwork/downloads/Builders_Guide_3_1.pdf
Peter

Using master socket to test Home Hub 2

I've been having problems with my broadband dropping out. I've tried 5 different ADSL filters so have now decided to test the hub using the master socket. I'm not wireless. My question is do I need to also connect the ethernet cable to the hub whilst testing or is it just the power and broadband cables? Thanks

Thanks for your help. I don't think the lead is going to reach my master socket from my pc so I suppose there's no other way of testing it.
Does anyone have the following problem:
When my connection drops, the only way I can keep it going is by making a phone call! I just dial 1471 and leave the line open. Not very satisfactory but at least it works lol.
I don't have any other electrical items in the room except the printer, I use a simple extension socket that seems ok and I've changed the ADSL filter - have tried 5 - and I'm now thinking of calling out an engineer but don't want to incur the £129.99 fee before I've completely eliminated internal wiring problems and thought that by doing the test it would tell me if my wiring was the problem and not something outside.

Jtag axi memory test tcl script

Hi
For interactive testing memory AXI bus via JTAG AXI master, I use commands:
create_hw_axi_txn wr_txn[get_hw_axis hw_axi_1] -address -data -len 16 -size 32 -type write
create_hw_axi_txn rd_txn [get_hw_axis hw_axi_1] -address -len 16 -size 32 -type read
run_hw_axi wr_txn rd_txn
which output results to stdout
I want to write tcl script for testing all Memory. I am beginner in TCL programming.
How to redirect result of Read transaction in internal variable for comparing read and write data?
Maybe there is script for testing memory
Alexandr

I dont if there is already tcl command to verify this but i will answer your question from tcl point of view
You can assign output to internal variable like
set b [create_hw_axi_txn rd_txn [get_hw_axis hw_axi_1] -address -len 16 -size 32 -type read]
Comapre b with the write data. To see the varible b rub command puts $b
To compare you can use below command . $b is read data 00000_11111 write data here
string compare $b 00000_11111
If this tcl command returns 0 means read data is equal to write data

PCIe/AXI to user logic addressing

Hi,
I’m using a Spartan-6 XC6SLX45T-FGG484-2 FPGA and I’m using the Xilinx Platform Studio.
I want a PCIe host pc to communicate with two instances of a third party IP core via AXI4 memory mapped.
The host PC performs PCIe write and read transactions. The AXI slave responds to these transactions:
The AXI slave receives the data the host pc sent, and forwards it to the third party IP core, for a write request. For a read request, the AXI slave reads the data from the third party IP core, and sends it via AXI to the PCIe host pc.
My design looks like this:
PCIe/AXI MM bridge <> AXI Interconnect <> AXI_to_User_Logic <> 3rd_party_IP_core_0
<> 3rd_party_IP_core_1
AXI_to_User_Logic is an AXI4 memory mapped slave with two address spaces, that was created with the Create & Import Peripheral Wizard.
My first question is:
I think the PCIe/AXI bridge should be the AXI Master, so do I need to connect only the M_AXI to the AXI bus, or do I have to connect S_AXI and/or S_AXI_CTL as well?
The next question is: how to set the addresses?
I’m not sure whether I understood how to do the addressing, so I’d like someone to verify that the addressing I made is right. If it’s wrong, please show me how it has to be done.
I want to send 32 bytes to each AXI address space of the AXI slave and read 32 bytes from each AXI address space of the Slave.
Addresses of PCIe/AXI bridge IP core:
PCIe/AXI bridge: AXI Device Base Address (C_Baseaddr) = ?
PCIe/AXI bridge: AXI Device High Address (C_Highaddr) = ?
These Addresses can only be set in the PCIe/AXI bridge, not in the Slave. What do they mean? How should they be set?
Write and Read 32 Bytes to/from two AXI address spaces means: PCIe BAR size = 32 Bytes *2*2 = 128 Bytes (?).
128 = 2^7 --> PCIe BAR needs the lower 7 Bits to be 0 --> The bridge’s parameter C_PCIEBAR _LEN_0 = 7
The PCIe BAR gets determined by the configuration software.
Do I need an AXI BAR in the bridge? I don’t think so, as I only want to use the AXI Master Interface, right?
PCIe/AXI bridge: AXI Base Address 0 (C_AXIBAR_0) = ?
PCIe/AXI bridge: AXI High Address 0 (C_AXIBAR_HIGHADDR_0) = ?
PCIe BAR 0 mapped from AXI BAR 0 (C_AXIBAR2PCIEBAR_0) = ?
This BAR is only needed, if the endpoint (AXI/PCIe bridge) wants to initiate a transaction to the root port (that’s what I read about it, in the Xilinx support forum). So I don’t need this, right?
AXI BAR 0 mapped from PCIe BAR 0 (C_PCIEBAR2AXIBAR_0) = 0000 0000
Addresses of the User Logic IP core:
AXI_to_User_Logic_0:Mem0    Base Address = 0000 0000
AXI_to_User_Logic_0:Mem0    High Address = 0000 001F
AXI_to_User_Logic_0:Mem1    Base Address = 0000 0020
AXI_to_User_Logic_0:Mem1    High Address = 0000 003F
--> Both address spaces are 32 Bytes.
Let’s say the configuration software set the PCIe BAR0 to 0x0100 0000.
If the User_logic’s BARs and the PCIEBAR2AXIBARs are configured like above, I can access the second axi address space by performing a PCIe transaction with PCIe Baseaddress = 0100 0020 which will result in an AXI request with address = 0x00000020. Is this right?
I appreciate any help,
Fabian

interconnect is when you have one master, multiple slaves or multiple masters, single slave or any combination of NxM connectivity. If you have a single master and a single slave then there is no need for an interconnect and you can connect your master to the slave directly.
If you want a master example, you can do "tools|create&package ip|create new ip" and create an ip with master interface. Then you can add your master state machine/controller inside.
Also keep in mind that if you want your master to talk to your own slave and DDR you need to either have two master interface in your IP block or add an interconnect to demux your master to two separate slaves.

Promoto to OD Master - errors in slapconfig.log and slapd.log

After a lot of promoting to OD Master and demoting to Standalone I have finally a OD Master that seems like it's working.
At least I can bind my clients to it and then (after reboot of the client) work with networked home-dirs Smile.
BUT I have a couple of entries in my logs that I have not seen in the testserver (I had no problems with setting up a testserver as an OD Master on a test-LAN…)
1. /Library/Logs/slapconfig.log:
Creating the keytab file
kadmin: No entry for principal xgrid/[email protected]
exists in keytab
WRFILE:/etc/krb5.keytab
kadmin: No entry for principal afpserver/[email protected]
exists in keytab
WRFILE:/etc/krb5.keytab
Creating the keytab file
kadmin: No entry for principal ldap/[email protected] exists
in keytab WRFILE:/etc/krb5.keytab
2006-03-13 22:59:23 +0100 - kerberosautoconfig command output:
The machine is standalone
Removing /Library/Preferences/edu.mit.Kerberos
2006-03-13 22:59:23 +0100 - kerberosautoconfig command failed with status 255
2006-03-13 22:59:23 +0100 - command: /usr/sbin/mkpassdb -kerberize
2006-03-13 22:59:23 +0100 - mkpassdb command output:
kadmin.local: unable to get default realm
kadmin.local: unable to get default realm
kadmin.local: unable to get default realm
2. /var/log/slapd.log:
Monday, March 13 2006 @ 05:09 pm CST
After a lot of promoting to OD Master and demoting to Standalone I have finally a OD Master that seems like it's working.
At least I can bind my clients to it and then (after reboot of the client) work with networked home-dirs Smile.
BUT I have a couple of entries in my logs that I have not seen in the testserver (I had no problems with setting up a testserver as an OD Master on a test-LAN…)
1. /Library/Logs/slapconfig.log:
Creating the keytab file
kadmin: No entry for principal xgrid/[email protected]
exists in keytab
WRFILE:/etc/krb5.keytab
kadmin: No entry for principal afpserver/[email protected]
exists in keytab
WRFILE:/etc/krb5.keytab
Creating the keytab file
kadmin: No entry for principal ldap/[email protected] exists
in keytab WRFILE:/etc/krb5.keytab
2006-03-13 22:59:23 +0100 - kerberosautoconfig command output:
The machine is standalone
Removing /Library/Preferences/edu.mit.Kerberos
2006-03-13 22:59:23 +0100 - kerberosautoconfig command failed with status 255
2006-03-13 22:59:23 +0100 - command: /usr/sbin/mkpassdb -kerberize
2006-03-13 22:59:23 +0100 - mkpassdb command output:
kadmin.local: unable to get default realm
kadmin.local: unable to get default realm
kadmin.local: unable to get default realm
2. /var/log/slapd.log:
Mar 13 23:01:00 server slapd[389]: Entry
(uid=untitled_1,cn=users,dc=server,dc=my-domain-name,dc=net):
object class 'posixAccount' requires attribute 'homeDirectory'\n
Mar 13 23:01:00 server slapd[389]: entry failed schema check: object class 'posixAccount'
requires attribute 'homeDirectory'\n
Mar 13 23:01:33 server slapd[389]: Entry
(uid=t2,cn=users,dc=server,dc=my-domain-name,dc=net): object
class 'posixAccount' requires attribute 'homeDirectory'\n
Mar 13 23:01:33 server slapd[389]: entry failed schema check: object class 'posixAccount'
requires attribute 'homeDirectory'\n
PS.:
- Just to be on the safe side I have batch-replaced the domain name with "my-domain-name" & "MY-DOMAIN-NAME"
- Some linebreaks have been added to the logs above to make the whole post more readable!
Before I made the (almost?) successfull promotion to OD Master I did:
- Make sure reverse DNS is working
- Made the server's Network Preferences DNS server point to 127.0.0.1
- Set the hostname via "sudo scutil --set HostName"
- /etc/hostconfig contains "HOSTNAME=-AUTOMATIC-"
- The server is running DNS, AFP, Web, MySQL & Mail
- How serious are the errors I can see in the logs?
- How an I fix them?
TIA From a Kerberos newbie (that had a lot of help from the O'reilly book "Mac OS X Panther Administration")
PS.: This question is also asked on the very informative site AFP548 so far with no replies:
http://www.afp548.com/forum/viewtopic.php?forum=39&showtopic=11693
G5 dual 2.0 GHz, Mac SE and a lot more Mac OS X (10.4.5)

the message "kadmin.local: unable to get default realm" indicates that your
/Library/Preferences/edu.mit.Kerberos file is missing or incorrect.
Using workgroup manager look at the KerberosClient record (you may need to go into the preferences and set the "show all records" checkbox), look in the XMLPlist attribute for an xml representation of the edu.mit.Kerberos file.
as root on the OD Master, run klist -k to view keytabs (there should be 3 mostly identical entries for each service)
also as root on the OD Master, run kadmin.local -q "listprincs" to view the principals in the kdc.
Hope this gets you started
- Leland
DP G4 Mac OS X (10.4.2)

How to call external js file to custom master page

Hi all,
I have created custom master page and i need to call external .js to master page. i tried every aspect of including this in master page. but this js is not running.
<script src="test.js" type="text/javascript"></script>
i have put the above calling js script to head tag.
And, When i am running the site, the js file is not loading.
How to load this js file to custom master page.
Thanks,
Rakesh

I have placed js file in same folder of custom master page.
This is quite annoying and i am struggling to call it.
js file is in same master page folder still i am calling it through whole URL as
<script type="text/javascript" language="javascript" src="http://SharePoint/sites/SiteName/_catalogs/masterpage/Master%20Page%20Template/test.js"></script>
Still it is not working.
Now i am not sure what is wrong here.
Please help..
Thanks in adv !!
Rakesh

Service product replication for test and developement system

Hi Experts,
In our scanario service product is created in production system and later manually created in test and developement system.
Is there is any standard function module avilable to replicate the product master data into test and developement system
Or Is it possible to use the middleware functionallity to replicate the service product details.
Please advice on this issue.
Thanks,
Senthil .R
Edited by: Senthil Vadivelan R on Dec 17, 2007 3:46 PM

You can use the FindFile method in the TS API:
FindFile Method
Syntax
Engine.FindFile ( fileToFind, absolutePath, userCancelled, promptOption = FindFile_PromptHonorUserPreference, srchListOption = FindFile_AddDirToSrchList_Ask, isCommand = False, [currentSequenceFile])
The function itself returns a boolean which indicates if the file exists or not.
Then just use a Call Executable step to run command line string to delete the file.
Hope this helps!
jigg
CTA, CLA
teststandhelp.com
~Will work for kudos and/or BBQ~

Axis receiver - WS-SECURITY problem

Hi all,
we need consume 3th party web service through AXIS adapter. This communication must be secured by certificate. We have imported certificate into keystore. Therefore there are needed WS-addressing and WS-security for SOAP request. We need use UsernameToken Timestamp and next sign following element in SOAP envelope: s:Body, o:UsernameToken, u:Timestamp, a:Action, a:ReplyTo, a:MessageID, a:To. Now we are able add UsernameToken, Timestamp and action addresing by adding modules in AXIS adapter. But we have problem sign needed elements.
Now we have following SOAP request
<soapenv:Envelope xmlns:soapenv="http://www.w3.org/2003/05/soap-envelope" xmlns:xsd="http://www.w3.org/2001/XMLSchema" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:wsa="http://schemas.xmlsoap.org/ws/2004/08/addressing">
<soapenv:Header>
    <wsse:Security xmlns:wsse="http://docs.oasis-open.org/wss/2004/01/oasis-200401-wss-wssecurity-secext-1.0.xsd" soapenv:mustUnderstand="true">
      <wsu:Timestamp xmlns:wsu="http://docs.oasis-open.org/wss/2004/01/oasis-200401-wss-wssecurity-utility-1.0.xsd" wsu:Id="Timestamp-24">
        <wsu:Created>2010-12-23T16:27:30.889Z</wsu:Created>
        <wsu:Expires>2010-12-23T16:32:30.889Z</wsu:Expires>
      </wsu:Timestamp>
      <wsse:UsernameToken xmlns:wsu="http://docs.oasis-open.org/wss/2004/01/oasis-200401-wss-wssecurity-utility-1.0.xsd" wsu:Id="UsernameToken-23">
        <wsse:Username>user</wsse:Username>
        <wsse:Password Type="http://docs.oasis-open.org/wss/2004/01/oasis-200401-wss-username-token-profile-1.0#PasswordText">Apassword</wsse:Password>
      </wsse:UsernameToken>
    </wsse:Security>
    <wsa:MessageID soapenv:mustUnderstand="false">uuid:8a0e7b40-0eb1-11e0-97ac-8e95546643d1</wsa:MessageID>
    <wsa:To soapenv:mustUnderstand="false">http://www.test.iszo.sk/interfaces/MeasuredValues/Service.svc</wsa:To>
    <wsa:Action soapenv:mustUnderstand="false">http://sfera.sk/ws/xmtrade/iszo/measuredvalues/services/2008/11/01/MeasuredValuesContract/Upload</wsa:Action>
    <wsa:From xmlns="http://schemas.xmlsoap.org/ws/2004/08/addressing" soapenv:mustUnderstand="false">
      <wsa:Address>http://schemas.xmlsoap.org/ws/2004/08/addressing/role/anonymous</wsa:Address>
    </wsa:From>
</soapenv:Header>
<soapenv:Body>
But we need also add Security token to SOAP request to sign needed elements (body, UsernameToken, Timestamp, etc.) as follow:
<soap:Envelope xmlns:ns="http://sfera.sk/ws/xmtrade/iszo/measuredvalues/services/2008/11/01" xmlns:ns1="http://sfera.sk/ws/xmtrade/iszo/common/types/espv1r1/2008/11/01" xmlns:soap="http://www.w3.org/2003/05/soap-envelope">
<soap:Header xmlns:wsa="http://schemas.xmlsoap.org/ws/2004/08/addressing">
    <wsse:Security xmlns:wsse="http://docs.oasis-open.org/wss/2004/01/oasis-200401-wss-wssecurity-secext-1.0.xsd">
      <wsse:BinarySecurityToken xmlns:wsu="http://docs.oasis-open.org/wss/2004/01/oasis-200401-wss-wssecurity-utility-1.0.xsd" EncodingType="http://docs.oasis-open.org/wss/2004/01/oasis-200401-wss-soap-message-security-1.0#Base64Binary" ValueType="http://docs.oasis-open.org/wss/2004/01/oasis-200401-wss-x509-token-profile-1.0#X509v3" wsu:Id="CertId-17206535">MIIEgDCCA .... FJSC+w==</wsse:BinarySecurityToken>
      <ds:Signature xmlns:ds="http://www.w3.org/2000/09/xmldsig#" Id="Signature-12725597">
        <ds:SignedInfo>
          <ds:CanonicalizationMethod Algorithm="http://www.w3.org/2001/10/xml-exc-c14n#"/>
          <ds:SignatureMethod Algorithm="http://www.w3.org/2000/09/xmldsig#rsa-sha1"/>
          <ds:Reference URI="#UsernameToken-23996530">
            <ds:Transforms>
              <ds:Transform Algorithm="http://www.w3.org/2001/10/xml-exc-c14n#"/>
            </ds:Transforms>
            <ds:DigestMethod Algorithm="http://www.w3.org/2000/09/xmldsig#sha1"/>
            <ds:DigestValue>TFzBLZTL5JrDmMJFc2FyJZnVJ3Q=</ds:DigestValue>
          </ds:Reference>
          <ds:Reference URI="#Timestamp-12575106">
            <ds:Transforms>
              <ds:Transform Algorithm="http://www.w3.org/2001/10/xml-exc-c14n#"/>
            </ds:Transforms>
            <ds:DigestMethod Algorithm="http://www.w3.org/2000/09/xmldsig#sha1"/>
            <ds:DigestValue>7/RY2vugAOvUkBK8PH8zELTUCPI=</ds:DigestValue>
          </ds:Reference>
          <ds:Reference URI="#id-21926836">
            <ds:Transforms>
Have anybody some idea or example to resolution this issue? Thanks a lot for your answers.
Regards, Zolo

Hello Zolo, I hope you are doing wellu2026
Iu2019m sending you some info that might help you with this matter.
1)
Please check:
Advanced usage questions
1.     How can I enable the WS-Security features?
Of note below:
1039369 - FAQ XI Axis Adapter
2)
Please test the SSL connection with "https://<servername>:<SSL port>".
If SSL is configured correctly, then the SAP J2EE Engineu2019s start page appears in your Web browser.
There shouldnu2019t be any "Security Alert" or warnings related with security.
3)
Please check the links below to gather further info in how to set up this scenario with certificates.
(The below links are for 7.1 systems, if you are on 7.0, just change /saphelp_nwpi71/ by /saphelp_nw70/).
Axis Framework in the SOAP adapter
http://help.sap.com/saphelp_nwpi71/helpdata/EN/45/a4f8bbdfdc0d36e10000000a114a6b/frameset.htm
Message-Level Security
http://help.sap.com/saphelp_nwpi71/helpdata/EN/a8/882a40ce93185de1000000
0a1550b0/frameset.htm
Security Configuration at Message Level
http://help.sap.com/saphelp_nwpi71/helpdata/EN/ea/c91141e109ef6fe1000000
0a1550b0/frameset.htm
HTTPS Configuration for Messaging
http://help.sap.com/saphelp_nwpi71/helpdata/EN/e8/1f1041a0f6f16fe1000000
0a1550b0/frameset.htm
4) go to:
http://host:port/XIAxisAdapter/MessageServlet
The page will display the versions of the deployed components, whether the required libraries are also deployed and if Axis adapter was successfully deployed in the system.
For more specific scenarios, e.g., WS-Security, WS-ReliableMessaging, it is also necessary to have the relevant optional components deployed. The page should show status OK when all the required components are available and otherwise status Error.
Cheers,
Jorge Eidelwein

Master role and derived role concept

Guys,
1) How to assign the organizational levels for the derived role?
Say for example, I have to create the derived roles with respect to the plant code.And after inheriting the tcodes ,authorizations from the master role , I noticed a pop up page with organizational level tabulation and I assigned the respective plant code there and in the same way for all the following derived roles.But the rest of the rows like company code,sales organization,distribution channel etc which are seen in the tabulation are left empty.I noticed that all the fields which are left empty in the org.levels of the derived roles are been filled up with the vaules of the corresponding master role org.level values when the derived button icon , which is seen under the authorization tab of master role is pressed.So pls let me know the correct procedure to assign.*Do we really need to maintain org.values for master roles?*
2) If a master role is transported to QA or PRD, will the derived role along with it move automatically?
3) Is master and derived role tested parallely in the QA system or first master role is tested ,followed by the derived role?
4) According to my understanding we dont assign any user to the master roles, but why do we move it to PRD?
Greatly appreciate for some body's help.

> 1) How to assign the organizational levels for the derived role?
> Say for example, I have to create the derived roles with respect to the plant code.And after inheriting the tcodes ,authorizations from the master role , I noticed a pop up page with organizational level tabulation and I assigned the respective plant code there and in the same way for all the following derived roles.But the rest of the rows like company code,sales organization,distribution channel etc which are seen in the tabulation are left empty.I noticed that all the fields which are left empty in the org.levels of the derived roles are been filled up with the vaules of the corresponding master role org.level values when the derived button icon , which is seen under the authorization tab of master role is pressed.So pls let me know the correct procedure to assign.*Do we really need to maintain org.values for master roles?*
Only if you assign the master roles to users. (and maybe for testing, see 3)
>
> 2) If a master role is transported to QA or PRD, will the derived role along with it move automatically?
Nope, but if one of it's derived roles is transported the master is automatically included in the transport. You'll have to make sure all derived roles are transported yourself.
>
> 3) Is master and derived role tested parallely in the QA system or first master role is tested ,followed by the derived role?
Best order is to do all unit testing wit the master, with all org levels at * and create the derived roles only when the master is tested and corrected to satisfaction. In that way the derived roles only have to be tested for organizational shielding.
>
> 4) According to my understanding we dont assign any user to the master roles, but why do we move it to PRD?
See 2, it goes there automatically. No choice.
Jurjen

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Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction

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http://imageshack.us/photo/my-images/30/pz6h.jpg/
http://imageshack.us/photo/my-images/11/8iy3.jpg/
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Right okay, BT said that the line had been reconnected.
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