NI5640R FPGA non-diagram component compilation timing error

I've tried to rebuild the NI5640R example "ni5640R Template" without adding or changing anything.
Got timing error (see below), saying that requirement missed by 0.16ns, because of some non-diagram components: /sDac0Reset, /aDac0Reset_or00001, /aDac0Reset. Xilinx options were set to "use recommended settings".
I've tried this several times, always getting almost the same result. Another example: requirements missed by 0.40ns, because of /sDacSimultReset, /aDac0Reset_or00001, /aDac0Reset. This is still with recommended settings.
Then I tried to compile with design strategy "Timing Performance". 5 out of 6 times compilation failed with timing violation 0.30-0.50ns.
Then I tried to compile with design strategy "Balanced". This time it failed only 2 times out of 6 with timing violation 0.02-0.04ns.
I guess using the "Balanced" strategy works more or less, but maybe there is some better way to address this? I don't even need DAC in my project, so maybe there is a way to exclude it?
Solved!
Go to Solution.

hey thu^^,
I tried this with LabVIEW2013, FPGA module, NI5640R v1.7 drivers, and successfully compiled the example template. I'm attatching my screenshots. Please let me know if there is any difference between my experiment and yours.
Attachments:
XilinxOptions.png ‏15 KB
compilationSummary.png ‏23 KB
finalTiming.png ‏24 KB

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Timing Error by non diagram component

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hey thu^^,
I tried this with LabVIEW2013, FPGA module, NI5640R v1.7 drivers, and successfully compiled the example template. I'm attatching my screenshots. Please let me know if there is any difference between my experiment and yours.
Attachments:
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compilationSummary.png ‏23 KB
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Compilation - Timing Error

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J'ai remarqué que de temps en temps, la compilation de mes VI FPGA se terminaient sur une "Transgression de cadencement" alors que toutes mes boucles sont cadencées...
La pluspart du temps, je relance la compilation juste derriere et elle se termine parfaitement bien. J'aimeraic quand même savoir d'où cette erreur peut venir et commment faire pour empecher qu'elle ne survienne trop souvent (ça fait quand même perdre 15mn...).
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Re-Bonjour,
Je viens de lancer la compilation d'un programme FPGA qui s'est arreter due à une "Erreur de cadencement". J'ai relancer la compilation car de temps en temps cela suffit mais au cas où, le VI est en piece jointe.
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Gabi Tillmann wrote:
Second thoughts:
Is it really worth using that so highly promoted FPGA on cRIO ???? We'll see.
This Question is technically wrong!
Whenever you are using the C-Series IO-Modules of the cRIO you are using the FPGA, even in ScanMode where NI RIO loads pre-defined bitfiles onto the FPGA.
The FPGA provides you ns Timing, it gives you nativly true parallelism, you are directly programming the bahaviour of FlipFlops, LUTs, Registers and so on.
It gives you the ability to programm hardware without the need to understand complex HDL languages.
The cRIO is besides PXI the most flexible and powerful (908x) platform NI offers. The decision to use an FPGA or to use a cRIO should not be "because it's there".
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/usr/local/natinst/NIFPGA/programs/xilinx14_4/ISE/bin/nt64/xtclsh
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