Ni5640R sync with external clock

Question

Hi,
I have a highly stable 10MHz sine source, and I need to phase-lock NI5640R's internal 200MHz generator to it.
I don't really understand half of the parameters in "Config Timebase". Any advice on how to do this?

Answer 1

As I understand it, in:
CDC Clock Source tab:
* Clock Source = VCXO, since I need not external clock, but internal oscillator locked on external signal
VCXO tab:
* VCXO Control = PLL, since VCXO frequency will be controlled by external clock via PLL
* VCXO Enable = ON, obviously
Reference tab:
* RTSI Ext Ref Enable = OFF
* SMB Ext Ref Enable = ON, since this is the external signal source
* Clk100 Ref Enable = OFF
* RTSI(7) Direction = OFF, don't know what it is, but doesn't seem relevant
PLL tab:
* Ref Delay = 0ps, I only care about phase stability at the moment, so delay is not relevant
* VCXO Delay = 0ps, same here
* Ref Divider = 10, this divides 10MHz external reference to get 1MHz
* VCXO Divider = 200, this divides 200MHz internal generator to get 1MHz, then both 1MHz freq's are synchronized
* CP Current = 2.5mA, but I have no idea what this does
* CP Enable = NO, no idea
* CP Invert = NO, no idea
* PFD Pulse Width = 1500ps, (CDC7005 datasheet states, that PFD pulse is something that improves spurious suppression) I have no idea how wide the PFD pulse should be, I guess it depends on external source quality
* Lock Detect Window = 1.2ns, as I understand it, PLL is considered locked when rising edge of controlled signal of is in this window, so smaller window means less jitter
Routing tab:
* PLL Feedback Channel = Y2, this is by default, I don't know if this should be touched. This is also a bit confusing, since the choice is between [Y0, Y1, Y2, Y3, Y4, Y3, Y3, Y3]. I wonder how these Y3's are different?
* Y0 (ADC0) Division = divide by 2, Y0 Enable = YES, I see no need to modify this
* Y1 (ADC1) Division = divide by 2, Y1 Enable = YES, same here
* Y2 (DAC0) Division = divide by 2, Y2 Enable = YES, same here
* Y3 (DAC1) Division = divide by 2, Y3 Enable = YES, same here
* Y4 (RTSI Ref) Division = divide by 2, Y4 Enable = YES, same here
Misc tab:
* OPA Enable = FALSE, OPA is a enable/disable control for amplifier. I'm not really sure about what it does and if this is even connected in NI5640R, default is off
* Enable Ext Ref R = FALSE, may be something related to what I need, by default it is off
* Hold = FALSE, as I understand, when this is enabled, PLL tries to maintain lock when missing reference cycle, probably may be used for clock extraction from serial data stream. for this application it's not necessary
* NPD = TRUE, according to CDC7005 datasheet, NPD is asynchronous power down, and should be held high
* NRESET = TRUE, asynchronous reset signal, should be held high
* Bandgap Enable = TRUE, not sure what bandgap is, and I don't think it's relevant
External tab:
* HW NPD = TRUE, should be hardware power down
* HW NRESET = TRUE, hardware reset