PCS PMA 1000Base-X Stuck in Reset

Question

We are trying to get some initial testing done with our Artix 7 15T using the 1000Base-X component.  We instantiated the PCS PMA in 1000Base-X mode using the GMII interface with the shared logic integrated into the component.  We have configured an MMCM for a 200MHz clock for the independent_clock input.  But the resetdone from the component never asserts.  After inserting some ILAs and digging around, the rxresetdone from the GTPE2_CHANNEL is never asserting.
I'm sure we've misconfigured/misconnected it somehow.  Here's our instantiated component, where:
reset_sys comes from an internall generated reset controller
mgtrefclk_p/n are the externanally connected differenctial 125MHz clock
eth_tx_n/p and eth_rx_n/p go to our magnetics
clk200 is from the internal MMCM driven by the gtrefclk_bufg output
CONFIGURATION is a constant set to "10000" (only autonegotiation is turned on)
PCS_PMA_AN_VEC is a constant set to advertise full-duplex
And the GMII pins are driven by our internal GMII component.
I've verified via an ILA that the GMII pins are wiggling as expected.  The GMII clock is wiggling fine, as is clk200.  But xcvr_reset_done never asserts.
Any insight would be greatly appreciated!
eth_driver : gig_ethernet_pcs_pma_0
port map
reset => reset_sys,
-- Reference clock
gtrefclk_p => mgtrefclk_p,
gtrefclk_n => mgtrefclk_n,
-- SFP interface
txn => eth_tx_n,
txp => eth_tx_p,
rxn => eth_rx_n,
rxp => eth_rx_p,
-- According to the documentation this needs to be a 200MHz clock.
-- We do this by taking gtrefclk_bufg_out to an MMCM to genreate the 200MHz.
gtrefclk_bufg_out => gtrefclk_bufg,
independent_clock_bufg => clk200,
userclk_out => open,
rxuserclk_out => open,
rxuserclk2_out => open,
resetdone => xcvr_reset_done,
pma_reset_out => open,
mmcm_locked_out => open,
-- GMII Interface
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
userclk2_out => gmii_txrxclk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_isolate => open,
configuration_vector => CONFIGURATION,
signal_detect => GND, -- Assume no signal
an_interrupt => open,
an_adv_config_vector => PCS_PMA_AN_VEC,
an_restart_config => GND,
-- Unused outputs
status_vector => open,
gtrefclk_out => open,
gt0_pll0outclk_out => open,
gt0_pll0outrefclk_out => open,
gt0_pll1outclk_out => open,
gt0_pll1outrefclk_out => open,
gt0_pll0lock_out => open,
gt0_pll0refclklost_out => open
);

Answer 1

Well, I solved it.  This line:
signal_detect => GND, -- Assume no signal
Was the culprit.  And from the documentation:
Note: When signal_detect is set to logic 0, this forces the receiver synchronization state machine of the core to remain in the loss of sync state.
And duh, I connected wrong.