PLCC-28 DRC Errors

Hey all, me and my work partner have a question since when we import the part PLCC-28 (This is just a differential clock driver) the part itself has DRC erros even though
is from the NI library!
Design Rule Error: Net VCC Close To Net 0
Design Rule Error: Net SMA20 Close To Unused Pin.
This is because the top right pin and right pin on top seem to be too close to each other....is there anyway this can be a mistake in the original package file...also I tried right clicking the
part and doing an in place part edit and I managed to move the pins a bit apart and then after I was done it showed no DRC errors...but the problem is you can move the pins around just like that right?
Any help would be great, let me know your thoughts on this.

Hi, Design Rules Check (DRC) errors are defined by the designer, not by NI. You start with a default global setting that may or may not be good for your design. One of the first steps when you transfer a design is to actually define your design rules along with many other things.
If two pins are too close together, and you are getting a DRC, go to View > Clearances and you will see that most likely the clearance area around those two nets are too close together, you might need to select the specific pin, right-click and select properties, then on the Pin Properties dialog select the General tab, look for the Clearance field and decrease it. Or use the Spreadsheet View to locate those pins (SMT Pads tab or THT Pads tab), then use the Trace Clearance column to decrease it.
DO NOT move the pins away, usually footprints are designed to match the actual part when placed, if you move the pins you might not be able to fit the part once you place it to solder it.
Nestor
National Instruments

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Keep out DRC error when placed under component body

I have several multiplexed displays and I don't want trace running under the displays, so I place a keep out rectangle in between all of the pins. Route the board, works as it should to 100%, but.....I'm getting a DRC red circle that says the component is within a keepout (it supposed to be!!). I've tried adding it as a part group, and tried to put it as an advanced option but the DRC remains.
What is the correct procedure to keep traces out from under a component without getting a keepout DRC error??????????????
Can't figure out what I'm missing here.
Signature: Looking for a footprint, component, model? Might be here > http://ni.kittmaster.com

Chris, you should not add the Part as a 'keepout' in the advanced options, you should add a Net Group instead... and in that net group include all nets... so you are doing a keepout area of all nets... not parts... with this solution you can draw the keep out shape under the footprint (but within the boundaries of the pads) and force the autorouter to avoid crossing under the display.
If you do not include any part groups in the advanced options of the Keep out area you will not get a DRC error for the part.
Nestor
National Instruments

UB12 DRC error filter manager doesn't save filters

In a PCB design, I have about 30 DRC errors that cannot be corrected due to the nature of the design (overlapping parts). These DRCs are listed in the results tab and the DRC tab of the spreadsheet view.
On the DRC tab of the spreadsheet view, If I right-click the DRC list and select add to filter, the DRCs disappear from the list, and the DRC markers disappear from the workspace. - Cool. I then switch to the results tab of the spreadsheet view, right click and clear the results list. Then I run the DRC and netlist check. Still no DRC markers in the workspace, no DRCs listed in the DRC tab of the spreadsheet view, no DRCs listed in the results tab of the spreadsheet view. Just a note about filtered DRCs.
I right click on the DRC list box in the spreadsheet view and select filter manager. Filter manager appears and the filter I just created is shown. I close the filter manager, then I save all and close UB.
I start UB again and open the same project and electronic design, the DRC markers show again in the workspace. However, the DRC errors are not listed in the DRC tab of the spreadsheet view. Even if I run a DRC and netlist check. However, the DRCs are listed in the results tab of the spreadsheet view. If I right click in the results list, I cannot filter the DRCs. If I right click in the DRC list I can select add to filter, but nothing happens. If I open the filter manager, no filter is shown. If I use the task bar to switch to another program, then switch back, that's when the DRC error re appear in the DRC list.
What's with this coo-coo behavior, and why doesn't the filter manager save my DRC filters?
Thanks
Regards,
Who

Hi,
The filters applied to the design should be removed everytime you re-open the design. These filters do not get saved along with the design. I tried out the filter manager and it seems to show the DRC errors right away after I re-open the design.
Hope this helps.
Regards,
Tayyab R,
National Instruments.

DRC error that I cannot fix

I have designed a 6 layer pcb in Ultiboard v10 and I am 100% complete according to the statistics. I have turned on "routable" for all layers of the design. The DRC check returns this error:
The object "Trace: Width(0.0250000 inch)Layer(Copper Inner 2)Clearance(0.0060000 inch) Net(48V) " Is on a layer that is not allowed by the net settings
This error repeats, with different objects, over 100 times. I can't seem to find the setting that will eliminate this error. My clearances are 0.006in for all instances. Any help will be much appreaciated. Thanks.

On the spreadsheet view go on the "nets" tab and locate the "routing Layers" column. The first number in the cell correspond to copper top, the second number correspond to inner layer 1 and etc... For example, if you see 10001 this means you are allowed to route on the copper top and copper bottom layer only and if there are traces on the inner layers it will result in a DRC message you mentioned. You can change all the nets setting by scrolling to the first net in the list and left click once and then scrolling to the last net on the list, hold the Shift key on your keyboard down and left click again. All the nets in the spreadsheet will be highlighted, now if you change one cell to 111111 (allow to route on all layers) all the other cell will change as well.
Tien
Tien P.
National Instruments

Urgent: Ultiboard consistently crashes on DRC check

On my design that is several months in the working I've reached a point where I don't get DRC errors anymore (even though I know there are several) and if I press the DRC check button manually ultiboard crashes. I've tested this on three of my coworkers computers and ultiboard crashes on everyone of them. This design is extremely urgent and I need to get help with fixing it immediately! For security reasons I cannot post the design here for everyone to see, but if someone is willing to help me then I can send the design file to him/her via mail.
Please help!
I will of course also speak to NI support but they are closed for the day in my country.
/Peter Hygren

Hi Peter:
Unfortunately, I cannot help you with your problem without the file. You may have already contacted support, but could you also email the file to me as soon as possible.
You can reach me by emailing [email protected] and putting the text "Forward to Garret" in the message header. Our technical support team knows how to reach me.
Garret
Senior Software Developer
National Instruments
Circuit Design Community and Blog
If someone helped you, let them know. Mark as solved or give a kudo.

DRC incorrectly shows Net to close to Net

Hi all!
I have this project which has Multisim as well as a Ultiboard project files.
Now I have drawn tracks from one SMT chip but DRC keeps telling me that a Net is to close to a Net.
I have verified that it comes under the error category "copper objects close to each other" because when I turn on that filter, all of my DRC errors disappear.
By default I've kept all clearances to 8 mils but I still get errors.
I have even set the clearances to 1 mil and done a "DRC and Netlist check" but the errors still show up.
Any genius knows which other setting/procedure can let Ultiboard recheck the copper clearances?
Please look at the images:
PCB view with DRC window showing errors. Note the red circles around the pins aswell as around some of the tracks.
PCB view with DRC window with filter "copper objects close to each other" enabled. Note the lack of errors!
Main menu > Options > PCB properties > Design rules tab. Note the clearances. Also view of the other Design rules when scrolled down.
Any help will be readily accepted!
Robin.
Attachments:
ultiboard 3.png ‏121 KB
ultiboard 1.png ‏107 KB
ultiboard 2.png ‏73 KB

Hey Kittmaster!
Thanks for your great tip! I did'nt understand (or discover) that the clearance was also a property that had to be set per trace. I thought it was a setting per PCB so I was frustrated that it did'nt work!
So now I have eliminated all the errors by doing what you said - the quick 'n dirty way - clicking on the Clearance column header and typing a value - 5 mils worked just right for me.
Oh and BTW, They have not used the Excel component becuase it is not possible to 'include' it in any app you want because MS does not freely package it as a COM/ActiveX control (not that I know of at least!) although there are a lot of 3rd party Grid controls available for use in any Windows/Web app.
Although you can write code to run in the Excel program - like scripts or extensions - or a full custom app - but understand that your program will run inside of Excel but Excel will not run inside an App.
If you feel that it is like Excel, these are just normal grid control functions - multiselect, multiedit etc.
I suss that the have built NI EWB tools in Visual C++ because it is usually the tool of choice for such hardcore CAD software running on Windows. Apple Mac has Xcode.
I know becuase I also happen to be a developer!
Have a nice day!

Net bridge design rule errors

Multisim 10.1.197 and Ultiboard 10.1.197
I could not get a net bridge to work in a Ultiboard layout, so I tried in a simplified circuit:
In Multisim, place a connector with several pins, for example HDR1X10.
Place a DGND and GROUND. Connect the first to pin 1. Connect the second to pin 5.
Transfer to Ultiboard
Rotate HDR1X10 so the pins numbers increment left to right
Place traces on the top layer so the pads of a net bridge connects one trace to another
Place a net bridge, picking GND and 0 (also tried 0 and GND)
This gives Design Rule Errors:
   Unused pin is connected to NET = GND
   Unused pin is connected to NET = 0
Is there a work around?
Ray

I am having the same problems. This is a very important feature that needs to work since there is no proper work around. This is always the case when there are ananlog and digital grounds that need to be kept separate, but also need to be connected somwhere in a very controlled fashion. I've followed the instructions exactly but what I get is a net bridge with no nets assigned to it's terminals. You can connect it up but you get the DRC errors as stated earlier.
This can be manually fixed by going into the netlist editor and selection each of the nets to be connected and adding on pin from the net bridge to each (NB1, pin _). This removes the DRC error and everything is happy.
The only problem is when you forward annotate again you lose the NB pin assignments and you have to edit the netlist again.
I tried a part in MS with the net bridge as the footprint, but UB will not impor the net bridge when you do that. To get around that I have a 'netconnect' part with just two dots and a silkscreen box around it. This can be placed where you want the bridge and will import each time. This is just a marker wheer you want the bridge to be. You still have to place the bridge manually and edit the netlist to fix the DRC error.
This is a bug. I should be able to assign the netbridge as the footprint of an MS symbol and have it come in with the right netlist connections when I forward annotate.   Alternatively, the netbridge assignments should be made to stick when the netlist is imported again.
David B

Design Rule Check Error

I have a component in my Multisim layout that has a package MINISOIC-10(MUB10A). It is for the audio amplifier LM4667MM. When the Multisim circuit is transferred to Ultiboard and the autoroute option is used it gives the error that nets are too close together. When finding these nets I find that it does not like how close the pins are from the component and therefore cannont find a route for the trace. I know this is the correct package so how do I get Ultiboard to realize the spacing between the nets for the pins cannot be changed.

Hi Hallee,
There is not much you can do about the pin locations and often sizes, if the pin default settings resulted in DRC errors where pins are too close, I would just set all pin clearances to 0, you can rely on the net settings for DRC check. You can double click on a pin and a pin properties dialog box should appear, under the "General" tab you can change the pins clearance. If you select all the pins, when you change one pin the other will change as well.
Tien P.
National Instruments

Copy Route Error

When I try to use the Copy Route function it does not work correctly. I select my source group and the previewed area is much larger than the desired source group. The copy route function appears to be selecting nearby vias that are not associated with that parts group. Has anyone seen this problem? It is very difficult to use the copy route function when you are always having to delete vias that become scattered over the board surface. Perhaps this is an issue NI needs to address in future versions.

Copy route is a complete PITA to use, I see it as a completely useless feature....
If you really want to replicate paths that are constant for what looks like some type of spectrum analyzer or equalizer filtering. I did the following:
Select the trace and via filters, disable all others......select trace area, copy > paste, the virtual outline will allow you to real time place the results and watch for any DRC errors in placement in real time, when happy release.....this pic took 12 seconds to do all 4.
Is this what you are trying to do?
Signature: Looking for a footprint, component, model? Might be here > http://ni.kittmaster.com
Attachments:
SS001.png ‏41 KB

My circuit goes convergence error and it is not simulating

hi!!!
im simulating this circuit...
then it just went to convergence error!!
and i alow it to solve it but it only consumes time and it cant fix the problem!!
the error came when i reset the display circuit!!!
can someone help me with this matter??
by the way im using circuit design suite 10.0.1!!
gud day!!
Attachments:
experiment ckt Vr1.ms10 ‏229 KB

O.K. I am going to tackle these as I get a solution for you or an explaination compiled.
1. I did manage to get the circuit simulating for the full time without convergence error. What I did was to take all the Analog components off of VCC and run them to the analog DC Power. I have found on a number of occassions that it is best to separate the analog components from the digital power sources and run them to their own DC Power Source to prevent problems when simulating. For some reason when you hook analog and digital components together on the schematic the simulator likes for each to be coupled to its appropriate power source otherwise it starts coughing up errors. As far as real time is concerned that is not possible with Multisim. You can get close, but you run the risk of timestep too small errors. It takes the simulator time to number crunch and it can't do that very fast. The larger the circuit the more real time it takes to simulate. On very large circuits it may take 1 minute of "real time" to simulate 1 second of circuit time. Basically it is the nature of the beast and there are very limitied options available to speed it up without it spitting errors at you. I will post the updated circuit for you to try.
2. DRC errors do not effect simulation. They are user adjustable and only there to advise you that, according to your settings, you have a wire connected where you didn't want it connected i.e DC voltage on a timer output. You can turn these on or off by going to TOOLS>ELECTRICAL RULES CHECK>ERC RULES and disbling the ones you want by turning them from red to green by clicking on the square.
Kittmaster's Component Database
http://ni.kittmaster.com
Have a Nice Day
Attachments:
experiment ckt Vr2.1.ms10 ‏200 KB

UNCONNECTED PINS ERROR

I am using MS9 and when i run the electrical rules check i get lots of unconnected pins errors/warnings.
I have checked the netlist for these pins and it seems that they are connected to the correct net as i had wanted.
this problem is making it very hard to find real connection errors.
is this a common problem or bug?
thanks in advance for any help...

If you look at U47 pin 3 for example, you have a wire connecting to the chip but that wire is just hanging there, node 3 does not connect to anything else in your schematic so this pin is not connected.
You can see from my example that I added another component and created a virtual node 3 connection and the DRC error circuit is gone for this pin.
Tien
Tien P.
National Instruments
Attachments:
Doc2.doc ‏24 KB

How can I design a single layer board in Ultiboard?

The students I work with design some very simple boards and we want to make them single layer, mainly because we etch them ourselves. Is it possible to set-up Ultiboard to route on a single layer?
Solved!
Go to Solution.

Ultiboard always has at least two layers, but you can turn off routing for individual layers. You will then get DRC errors for any copper on the "off" layers.
Open the design
Click Options > PCB Properties and select the Copper layers tab
In the Allow routing box, change the layer name Copper Bottom, and click Properties
In the Copper Layers Properties dialog, uncheck Routing. It should look like the image below
Garret
Senior Software Developer
National Instruments
Circuit Design Community and Blog
If someone helped you, let them know. Mark as solved or give a kudo.

Here we go again...autorouter getting worse!

I doing a tight quarter remote wireless controller and it can't get to 100% as usual.
This problem was supposed to be fixed in 8, 9, and now 10.....the autorouter shapes are not passing from UB to the autorouter!!!!
Example, I'm using square pads in the pcb design but the router is showing and routing around ROUND shapes.....this is something tien and braulio put in as a bug even during BETA stages......why is this problem STILL around!
Router can finish because the shape passing still is as it should be and these parts are taken from the master database!!
Solutions?
Signature: Looking for a footprint, component, model? Might be here > http://ni.kittmaster.com

Chris,
Ok, I checked the file, and I talked to R&D... I will post this same message also in your other post.
So, there are two issues here that I will note separately...
1. Turning square pads into circular pads "during" routing is a cosmetic issue only, it is fixed in our internal build and is on hold to be verified on our next update or release (you can reference this report with us in the future with ID 105795). Once you finish routing, the pad shape returns to the original square. Internally, the autorouter never changes the shape for the pad, is only the graphics engine that is drawing the shape for you to see it on screen while is routing.
2. DRC errors when finished. This is independent from the shape problem you see, and has to do with the autorouter itself overriding clearances when routing in some places. R&D is actively working to improve the autorouter and avoid this, currently you need to manually move the trace where a DRC error shows up after routing.
This is the status update on these issues...
Nestor
National Instruments

Need help to interface InRevium's TB-FMCH-HDMI4K Board with ZC706 Eval board

We (PathPartner Technology Consulting Services) have recently procured the above-mentioned card(from Inrevium) for supporting HDMI display (HDMI2.0 for 4K) for our FPGA-based Video Codec solution.
We are implementing this solution on ZC706 board (Zynq-7045 based)
We did get access to reference designs from Xilinx’s HDMI Reference Design lounge wherein the Reference design is targeted for KC705 evaluation board. It seemed feasible to implement the same design on ZC706 board since both the devices in KC705 and ZC706 use the same XCVR.
While implementing the design on ZC706 board, we could not generate bitfiles due to DRC violations. We did set the pin assignments made in XDC file targetting ZC706 (compared to KC705).
The DRC errors are:
[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed. The problem bus(es) and/or net(s) are IPI_INST/hdmi_ipi_i/hdmi_gt_0/inst/drurefclk_to_qpll.
[DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 2 out of 49 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DRU_CLK_P_IN, DRU_CLK_N_IN.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
Delving further:
The HDMI 2.0 Design requires GT differential clock pairs for 3 of its clocks, the pins are as mentioned below:
In the reference design that is based on the KC705 board, these pins are connected to the approriate GT Differential clock pairs as below:
set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN] (FMC_HPC_GBTCLK0_M2C_P on KC705)
set_property PACKAGE_PIN G8[get_ports DRU_CLK_P_IN] (SMA_MGT_REFCLK_P on KC705)
set_property PACKAGE_PIN E8 [get_ports TX_REFCLK_P_IN] (FMC_HPC_GBTCLK1_M2C_P on KC705)
But in case of ZC706 we could find only 2 GT pairs: FMC_HPC_GBTCLK0_M2C and FMC_HPC_GBTCLK1_M2C that corresponds to pins AD10 and AA8 respectively.
We could not find another differential clock pin on HPC connector with similar properties for DRU_CLK_P_IN.
We have set the constraints as follows:
set_property PACKAGE_PIN AD10 [get_ports HDMI_RX_CLK_P_IN]
set_property PACKAGE_PIN AA8 [get_ports TX_REFCLK_P_IN]
and
set_property PACKAGE_PIN AF10 [get_ports DRU_CLK_P_IN]: Need to find an appropriate pin on ZC706 board
Please refer to the attached .xdc file that we are using for the bit file generation on ZC706 board (we have retained the file name similar to one used for KC705 in the reference design).
It will help us if we can find an alternative pin for the DRU_CLK_P_IN on ZCZ706 board
Another alternative would be: We do not need the RX port. Hence, if RX can be completely disabled, the RX CLK pin can be used for DRU_CLK_P_IN. Need to know how RX can be disabled.
Looking forward for guidance in resolving the above-mentioned...
Thanks and Regards
Lalith

Hi Satish,
For the TB-FMCH-HDMI4K Card that we have procured from InRevium, we have got a reference design that is targetted for KC705 board. We have a ZC706 board and intend to get this card operational on ZC706. It seemed feasible since both the devices in KC705 and ZC706 use the same XCVR.
The HDMI 2.0 Design requires GT differential clock pairs for 3 of its clocks, the pins are as mentioned below:
In the reference design that is based on the KC705 board, these pins are connected to the approriate GT Differential clock pairs as below:
set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN] (FMC_HPC_GBTCLK0_M2C_P on KC705)
set_property PACKAGE_PIN G8[get_ports DRU_CLK_P_IN] (SMA_MGT_REFCLK_P on KC705)
set_property PACKAGE_PIN E8 [get_ports TX_REFCLK_P_IN] (FMC_HPC_GBTCLK1_M2C_P on KC705)
But in case of ZC706 we could find only 2 GT pairs: FMC_HPC_GBTCLK0_M2C and FMC_HPC_GBTCLK1_M2C that corresponds to pins AD10 and AA8 respectively.
We could not find another differential clock pin on HPC connector with similar properties for DRU_CLK_P_IN.
We have set the constraints as follows:
set_property PACKAGE_PIN AD10 [get_ports HDMI_RX_CLK_P_IN]
set_property PACKAGE_PIN AA8 [get_ports TX_REFCLK_P_IN]
and
set_property PACKAGE_PIN AF10 [get_ports DRU_CLK_P_IN]: Need to find an appropriate pin on ZC706 board
Please refer to the attached .xdc file that we are using for the bit file generation.
It will help us if we can find an alternative pin for the DRU_CLK_P_IN on ZCZ706 board
Another alternative would be: We do not need the RX port. Hence, if RX can be completely disabled, the RX CLK pin can be used for DRU_CLK_P_IN. Need to know how RX can be disabled.
Looking forward for your guidance in resolving the same
Thanks and Regards
Lalith

Ultiboard - connecting pins to each other on footprint

I have a shielded connector with two mounting screws. Both screws are connected to the shield, so if I want to ground it I only have to connect my GND net to one of the hole pads. It doesn't matter which one, because they are common to the shield.
My setup:
In Ultiboard, the footprint has two pads - one for each of the mounting screws.
In Multisim, my symbol has one pin for the shield. I've mapped that pin to both of the Ultiboard footprint pads.
Now my problem:
In Ultiboard, the GND net connects to both of the footprint pads. I've attached one to a GND trace, but not the other. So Ultiboard constantly throws a DRC error because I have a pin that's not connected. I know that I can manually disconnect the pin from the net, but I think there must be a way of doing this automatically. What I mean is, how can I group two pins together on the footprint so that either one can be used to connect to a net? Maybe this is pin swapping, but it looks to me like I can only do pin swapping in Multisim and then only if my symbol has multiple pins that are the same. I have a few components like this, and I want to set them up in the database so that when you place them on a board, you don't have to manually remove any pins.
I'd appreciate any advice. Thanks so much.

From the point of view of EMC, it is NOT advisable to connect only one pin of a connector housing to GND. Connecting all pins will yield lowest impedance between any point of the housing and GND. Even if you measure 0 ohms with an ohmmeter (which uses DC for measurement), this does not mean that the impedance is just as low for RF, or in other words, there might be (unnecessary and unwanted) inductivity.
"Pin swapping" means that you can swap pins, say, of a multiple-input AND gate. If you see that it would be more convenient to connect a different input to a certain signal than indicated in the schematics, you can swap the input in questions with another one. You will have to re-annotate this from the board to the schematics.

PLCC-28 DRC Errors

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