Poor clock signal on REQ lines

I'm using a 6435 board to output digital patterns to my peripheral device. I'm using the REQ1 pin of my I/O connector for my peripheral's clock signal. When outputting my data, the clock signal looks really poor. I'm trying to get a clock speed of 5-10 Mhz. For that type of speed, what range of rise time should my eqipment be capable of for the clock? I'm also seeing a poor duty cycle, how can I get it close to 50%? I'm using my 6534 in a PXI chasis.
Thanks,
Sal

When generating an internal REQ signal, the asserted time of the resulting clock will be one period of the timebase used to generate the REQ.
REQ Pulse Width = 1 / Timebase Frequency
The timebase frequencies available for the 653x boards are: 20 MHz, 10 MHz, 1 MHz, 100 kHz, 10 kHz, 1 kHz and 100 Hz.
The transfer rate is equal to the timebase frequency / timebase divisor. The timebase divisor can be any integer from 2 to 65,355. With a timebase of 20 MHz, the divisor can be set to 1.
Transfer Rate = Timebase Frequency / Timebase Divisor
A timebase frequency of 100 kHz and a timebase divisor of 25 will give you a transfer rate of 4 kHz and a pulse width of 0.01 ms.
REQ Pulse Width = 1 / 100kHz = 0.01ms
Transfer Rate = 100kHz / 25 = 4kHz
I
n LabVIEW, you can set these two parameters by using the Digital Clock Config VI. In CVI, this is done with the DIG_Block_PG_Config function, where the "timebase" parameter is the timebase frequency, and the "reqInterval" is the timebase divisor.
Brian

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