Labview FPGA 2012 - Clock Signal

I'm trying to access the FPGA clock signal in Labview 2012. I have a NI PCIe-7852R card, with which I'm using the 40MHz onboard clock signal. I'd like to use that signal to clock some logic in my design, but there seems to be no easy way to access it - or, at least, the "clock signal" component has its own data type which only connects to a timed loop (the logic in question is in the form of a VHDL black box, which requires multiple clock rates; therefore since the IP integration node only allows one signal to be tied to the clock I need others as well, which will be fractions of the onboard clock). Any advice?

I use a SCTL running @ 20MHz to generate a 10MHz clock.
All you need is a SCTL with an Invertor on the IO Line and shift registers to hold the last state of the IO.
Each time the SCTL runs the IO is inverted and output. You should be a 50% Duty Cycle Clock.
Visualize the Solution
CLA
LabVIEW, LabVIEW FPGA

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    Intaris
    Trusted Enthusiast
    Posts: 3,264
    Re: LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
    ‎10-28-2014 12:11 PM
    Just out of interest, what is the resource usage differential between the two versions?
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    I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml,  Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
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    Please I need speedy help.Thanking in you in anticipation.
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    XilinxLog.txt ‏256 KB
    labview project files.zip ‏51 KB

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