Problem with LogicCore clocking wizard

Question

Hi,
i got this error during the translate of my design but i can't understand the reason of it:
ERROR:NgdBuild:455 - logical net 'CLK_OUT2_SIGNAL' has multiple driver(s):
ERROR:NgdBuild:455 - logical net 'CLK_OUT3_SIGNAL' has multiple driver(s):
I'm using ISE 14.7 and the IP clocking wizard 3.6, which menages 3 clock signals: two of them are the clock for other IP cores (selectIO interface wizard) and the third drives the clock for a counter and a ROM.
here is the code of the top level entity:
entity strutturale_SERDES is
port(
clk,
reset,
control : in std_logic;
output : out std_logic_vector (7 downto 0)
end strutturale_SERDES;
architecture Behavioral of strutturale_SERDES is
signal output_ser : std_logic_vector (0 downto 0);
signal CLK_DIV_OUT_deser_signal : std_logic;
signal CLK_OUT2_SIGNAL : std_logic;
signal CLK_OUT3_SIGNAL : std_logic;
signal CLK_OUT1_SIGNAL : std_logic;
signal CLKFB_IN_SIGNAL : std_logic;
component DESER is
generic
 (-- width of the data for the system
  sys_w       : integer := 1;
  -- width of the data for the device
  dev_w       : integer := 8);
port
  DATA_IN_FROM_PINS       : in    std_logic_vector(sys_w-1 downto 0);
  DATA_IN_TO_DEVICE       : out   std_logic_vector(dev_w-1 downto 0);
  CLK_IN                  : in    std_logic;                    -- Single ended Fast clock from IOB
  CLK_DIV_OUT             : out   std_logic;                    -- Slow clock output
  IO_RESET                : in    std_logic);                   -- Reset signal for IO circuit
end component;
component strutturale_SER
is port (
clk_ser,
clk_signal_gen,
reset,
control : in std_logic;
output : out std_logic_vector (0 downto 0)
end component;
--ipCore Clocking Wizard
component Multiplatore_CLK is 
port
 (-- Clock in ports
  CLK_IN1           : in     std_logic;
  CLKFB_IN          : in     std_logic;
  -- Clock out ports
  CLK_OUT1          : out    std_logic;
  CLK_OUT2          : out    std_logic;
  CLK_OUT3          : out    std_logic;
  CLKFB_OUT         : out    std_logic;
  -- Status and control signals
  RESET             : in     std_logic
end component;
begin
U1: DESER port map (
DATA_IN_FROM_PINS => output_ser,
DATA_IN_TO_DEVICE => output,
CLK_IN => CLK_OUT3_SIGNAL  ,  --clk for one IP core (selectIO interface wizard)
CLK_DIV_OUT => CLK_DIV_OUT_deser_signal,
IO_RESET  => reset
U2: strutturale_SER  port map (
clk_ser => CLK_OUT2_SIGNAL, --clk for one IP core (selectIO interface wizard)
clk_signal_gen =>  CLK_OUT1_SIGNAL , --clk for the counter and the ROM
reset => reset,
control => control,
output => output_ser
 --ipCore Clocking Wizard
U3: Multiplatore_CLK port map (
 CLK_IN1  => clk,
  -- Clock out ports
  CLK_OUT1=>CLK_OUT1_SIGNAL,
  CLK_OUT2=>CLK_OUT2_SIGNAL,
  CLK_OUT3=>CLK_OUT3_SIGNAL,
  CLKFB_IN=>CLKFB_IN_SIGNAL,
  CLKFB_OUT => CLKFB_IN_SIGNAL,
  RESET=>reset
end Behavioral;
I thank you in advance for your sopport.

Answer 1

No i didn't try an example design.
I resolved the problem using  the buffers of the kind BUFPLL.
Thank you