Hold time problems with Dual Clock FIFO

Question

Undoubtedly the main use-case for Dual Clock FIFOs is the transport of data across clock domains.
In this simple example, a serial datastream is deserialized and written to a dual clock FIFO, which in turn is read in a different (slightly faster) clock domain by a simple loopback unit, which takes the data and sends it back through another dual clock FIFO, where it is read and serialized out again.
The clock rates used are relatively slow (10Mhz and 12MHz) compared to the FPGA capabilities (both fabric and FIFO), so I would expect this to be straight forward and without any issues. Nevertheless, Vivado constantly creates a number of hold time violations on the input of the output FIFO (usually a few hundred picoseconds) where the routing delay seems to be in the range of 5ns, which I consider odd, given that both clocks have a period which is a magnitude higher.
The loopback should be synchronous with one clock cycle delay, so I wouldn't expect any problems from there.
As usual, I'm probably missing the obvious here and I'm looking forward to a great explanation what I did wrong :)
Thanks in advance,
Herbert

Answer 1

Here is the Timing Report.
The issue might be caused by the Quick directive given for place and route.
  place_design -directive Quick
  route_design -directive Quick
At least the hold time violations in this example go away when I remove the directive.
Thanks for looking into it, appreciated!
Best,
Herbert