ROT button DE FPGA

Hi everyone,
I am using LabVIEW FPGA board. I tried to use rotary button on the board but I can't find the ROT CENTER (or ROT A, ROT B) in the New FPGA I/O. Please help me indicate the problem.
Thank you so much
Mina
---Let it works---

First, make sure you've got the specific driver for that board. If you're trying to get this example up and running (since it refers to ROT A, B and Center) I can see that it was written for a slightly different board (the Digilent S3E Board) that has direct I/O for channels named ROT_A, B, and Center for a built-in encoder knob. For the NI Digital Electronics FPGA Board there are a couple things to know. First, the rotary knob on the board itself is not an encoder as described on page 2-11 of the user's manual. Rather, it is a control for a clock output and is not connected to the FPGA at all. There is a hardware add-on module from Digilent called the PmodENC Rotary Encoder Module that can plug in to the PMOD port on the NI board. If this device is plugged in to PMOD1 (aka J1 in the project) you can access its I/O lines in your project by going to New>>FPGA I/O>>Pmod Connectors>>J1:1-4 or J1:7-10. Once you've added these to the project you can rename them to anything you like, such as ROT_A or ROT_B.
Tim W.
Applications Engineering
National Instruments
http://www.ni.com/support

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Run error while loading FPGA host vi

Hi,
I want to use the NI-5640R board and have LV-FPGA installed together with LV 8.2...I have followed the post at :
http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=55
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http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=131
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Now, when I open up an existing example project (Single Tone Output), open up the Host Block diagram, I see the run button broken with some errors on the Thernal Shutdown subVi...
A software component for your target was not found. Make sure all target files are installed from the target installation CD. Error details:
Error 1059 occurred at New VI Object in StockFPGA_IntfScriptSubVI.vi:4->StockFPGA_ScriptMethod_Reset.vi:1->nirviCallScriptMethPlugin.vi->nirviMethod.xnode:nirviMethod_GenerateCode.vi:1->nirviMethod.xnode:nirviMethod_GenerateCode.vi.ProxyCaller
Possible reason(s):
LabVIEW: Unexpected file type.
I understand that the installation might not be correct ? Any clues on what is missing...
-thanks
anshuman

Hi
Did you do the last step?:
2. Run ...\LabVIEW 8.2\Targets\NI\FPGA\bin\lvfpga_make_resource_cache.exe
On this page?:
http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=131
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How can we deal with Button group

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import java.awt.*;
import javax.swing.*;
import javax.swing.border.*;
import java.awt.event.*;
import javax.swing.BoxLayout.*;
import java.text.*;
import java.util.*;
public class gender1 extends JFrame implements ActionListener
JPanel buttonpanel=new JPanel(),
private JPanel mainpanel=new JPanel(new BorderLayout());
private JButton Submit=new JButton("SUBMIT");
private JButton Update=new JButton("Update");
private JRadioButton gender[]=new JRadioButton[genderOptions];
private String genderlabels[]={"female","male"};
private JTextField malefield=new JTextField(10),
femalefield=new JTextField(10);
public gender1()
          this.getContentPane().setLayout(new BorderLayout());
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          initGender();
public void updatetotal()
//adding buttons and actionlisteners
lpanel.add(Update);
Update.addActionListener(this);
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Submit.addActionListener(this);
//adding textfileds for totals
lpanel.add(totmale);
lpanel.add(totfemale);
mainpanel.add(lpanel,"Center");
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buttonpanel.setBackground(Color.red.darker());
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//get teh one button which is selected
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if(gender[].getSelected()=="male")
int mtot,ftot=0
mtot=tot+1;
     int maletotal=maletotal+mtot;
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ftot=ftot+1;
int femaletotal=femaletotal+ftot;
femalefield=totfemale.setText(femaletotal);
malefield=totmale.setText(maletotal);
if(e.getSource==submit)
DataOutputStream dos=new DataOutputStream(FileOutputStream(gen))
dos.writeInt(maletotal);
dos.writeInt(femaletotal);
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gender c=new gender();
c.setSize(800,600);
c.setVisible(true);
c.addWindowListener(new WindowAdapter(){
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Is this the way to deal it?????

I use something like this in one of my GUI's
boolean female = false;
add a listener to the radio buttons and toggle the flag between true and false;
set the radio button to male as selected or female which ever is pc at the moment.
Jim

How to create a pushbutton delay in the FPGA module in Labview 8.2

I am a very inexperienced programmer of Labview, and I have what I thought would be a simple problem. I have a CompactRIO system that utilizes Labview 8.2 as well as RT and FPGA modules. I am running an end of line tester that uses a pushbutton to start the test. I am looking to force an operator to hold the test start pushbutton for one second before testing begins. If the pushbutton is released before the second is up, the test will not start. In the FPGA module, I cannot figure out how to accomplish this. I have tried using both flat sequence and while loops, but I cannot get the program to work as stated above. With the flat sequence there is not a way, that I could see, to break out of the sequence should the pushbutton be released. Using the while loop, I was closer to a solution, but could not get the program to read the input consistently. I did verify that the 24Vdc signal is getting to the input card whenever the pushbutton is pressed. The program worked fine without trying to add the delay when I was just looking for a transistion to 24Vdc on the input card when the pushbutton was pressed.
Any ideas? Thanks!

Here's how you might do it with a button on-screen in LabVIEW for Windows. If you need more specific help, post your code, or a small portion of it that demonstrates the bit that you can't get working. (The snippet is in LabVIEW 2009 since that's what I'm using, but the attached VI is saved for 8.2)
Attachments:
Hold 1 Second.vi ‏8 KB

LV 8.6: programatically pressing button only works in some VIs, not all?

Setup is an old labview 8.6
I'm tasked with fixing some strange old engine test bench which has a ~1E-6 measurement drift.
The "easiest" work around fix would be to run the mechanics to a bottom end point then press the "reset" measurement button automatically.
!!: A "drive" vi and a "measurement" vi has to be running at the same time. The drive vi will then periodically drive the test bench to a mechanical end point and reset the measurement vi. This would get rid of the drift.
!!: Both vi's must be started manually and running. I cannot start one vi from the other. It messes things up. I know not why. There seems to be some strange dependency over compiled FPGA code somewhere.
I'm no lab view wizard. It was 20 years since I touched it last.
So digging through examples on how to press a button in one VI from another VI I found this:
https://decibel.ni.com/content/docs/DOC-15962
Which I built into a sub-vi and a test setup to see if I could make it work on the test bench. With some tweaking it works.
A test "master" vi can press any button in a test "slave" vi.
However. It is impossible to press the "reset" button in the "measurement" vi.
Labview reports no errors, it just doesn't execute the value change event as far as I can understand.
In fact, I can copy exactly the same code from the working "slave" vi into the "measurement" vi and it stops working. !!??
How can code work perfectly well in one vi but not in another ?
The "measurement" vi has some sort of compilation requirements, meaning any change to the vi takes >30min to "compile" before it can be run. Can this have something to do with why remote button pressing doesn't work?
It also interfaces with some FPGA somewhere, can that have something to do with it ?
I have no clue. Happy for any help here.

Here it comes -- WARNING -- ugly code, this is my first labview in 20 years and I'm very short on time.
press-button.vi
the sub vi I mangle up from the example (https://decibel.ni.com/content/docs/DOC-15962)
master.vi
the test event sender
slave.vi
the test event receiver
measurement.vi
the real vi, where no buttons can be pressed
In master.vi you can reconfigure the input to press-button to which vi and button to target. Right now it is set for the test slave vi (I think) to verify that it actually works as intended in the test environment.
Hmm, seems there is a limit to 3 attachments, will post the measurement.vi in next post
Attachments:
press-button.vi ‏15 KB
master.vi ‏19 KB
slave.vi ‏29 KB

Programmatically calling an FPGA vi to view over the FP vi

Good morning. I have become stumped on this question for a bit so I thought I would post the question here.
Q: what is the best way to programmatically call a VI running on the FPGA to the FP main VI running on a touchscreen computer, where when the FPGA VI is called it goes to the top level of the screen without interrupting the VI output of the main VI?
I have researched using a queued message handler but couldn't get it to function properly. I have also researched dynamically calling a VI and asynchronously calling a VI but am unsure how to implement the correct one for what I are trying to accomplish.
What I am trying to overcome here has to a lot with tab control on the front panel VI as I have discovered that apparently while a tab is open to the top of the FP the other tabs do not I/O any values to the cRIO. This is good and bad for our application. The good part is that it allows a 'locking out' of other processes while the visible tab is on top. But the bad part is that if I open another tab then what I have running on the previous tab stops. I need to be able to incorporate both of these aspects in our program.
This example shows how I am using tabs in our program. (ATTACHMENT 1)
So in the example above, when page 5 is opened the graph indicator starts which is what I need, and when it closes it stops which is correct to.
But the issue is that when page 5 is open it also stops what’s happening on the other four tabs in the same tab pane which is NOT what I need to happen.
What I have done so far to correct this is - removing the page I need to open on top and made it into its own VI.
What this separate VI does is accept input from the FPGA resources including J1939 engine information through an NI9862 card and voltage / analog signals from sensors via an NI9207 card and reads the information on virtual indicators and gauges as seen here. So it makes sense to me to put the VI on the FPGA. (JPEG)
The information on this VI only needs to be seen periodically via the FP by the operator as it is called via a Boolean control (button) on the FP, but it still needs to run on the FPGA when not seen in order to pass information to the RT control for alarm processing. So in that, in the case of an alarm it causes something else to happen to the unit being controlled (ie. Execute an engine shutdown over the J1939 bus)
What this VI cannot do is interrupt the operations that are being executed by the main VI on the FP if called (to do a parameter check) but put the main VI into a ‘locked out’ mode if there is an alarm.
So then the question becomes how to call this VI from the Front Panel VI?
Well, I have tried to make a Queued Message Handler work which it did partially (I was able to open the VI and run it but I couldn’t work out how to close it) and unfortunately I have sub-sequentially erased that bit of programming code. Though I don’t think it would have worked anyway as I was trying to call it as a sub-vi in the main VI that was located on the computer and not on the FPGA target.
Then I tried dynamically calling the VI and found it did the same thing as if the VI were still connected to the tab control by stopping the I/O of the main VI while it was called to the front. I erased that bit of code work too.
So then I started looking at asynchronously calling the VI as I saw that it would allow both VI’s to run at the same time. Here I seem to have found the right answer to my own question, though, I believe that the example program I am looking at has a memory leak or is not closing out the called VI properly because within a few minutes runtime both VI’s slow to a stop. This is not good. I understand what the example code is trying to show but I don’t think it is programmatically correct and I have not been able to fix it. Here is the example code I was looking at. (ZIP FILE)
So while I believe I am on the right path I am not sure how to impliment it with the FPGA.
Solved!
Go to Solution.
Attachments:
Ultimate Tab Control.vi ‏32 KB
ENGINEVI.jpg ‏384 KB
example.zip ‏26 KB

You are correct, that is how the program is built. Each page of the tab has it's own set parameters to interact with the FPGA differently. (ie electromechanical controlling a hydraulic pump so each page has a distinct set of limitations on what the pump control does) this effectively creates a set of 'modes' for different parameter pump control to the same individual pump.
Here is a screen of the main program. The buttons at the bottom determine which mode the pump is in (effectively changes the tab control to a different tab)
So yes, the engine page has been removed from the tab control and made into it's own vi that I want to put on the FPGA target (as its only input and no interaction) but I want to be able to call the engine vi from the main program and not interrupt the main program if I am controlling the pump but just want to see what the engine and pressures are doing.
I added a screen of some of the code tied to the picture above.
Attachments:
virun.jpg ‏226 KB
Untitled2.png ‏148 KB

FPGA: 2-D arrays supported?

I'm getting an error in an FPGA VI when editing the VI (broken run button): "Maximum number of array dimensions exceeded for target" The array is 8x16 boolean. Doesn't the target support 2-D arrays? My target is cRIO-9102. I tried to make the control smaller, too, but without success.
Thanks,
Rob
Rob
LV2011,LV2012,LV2013

anderson1988 wrote:
Hi, I am experiencing a similar problem with my NI PXI 7833 and fpga module. I need to burn a code which inherently contains boolean 2D arrays in it. I am looking for effective ways to express a 2d array as a 1d array... if you have succeded in doing so kindly reply... your help shall be greatly appreciated.
cheers
Sid
If you want to do it mathematically (I did this in the past in BASIC - yes, I've been around that long), then store everything in a one-dimensional array and calculate the index into that array.
Example: if you have two dimensions (X,Y) and the Y dimension is of a maximum size of Z, then the index into the one dimensional array would be X * Z + Y.
This should work well with LabVIEW since it starts all indices at 0.
I hope this helps and that you can get it working.
Rob

FPGA Compile Error: Timing Violation

All,
I've got an issue here I've been struggling with for a couple days now. I'm trying to implement a very watered down Kalman filter in the FPGA (I wanted it to run faster than I had it running in the RT.) After quite a bit of optimization, I'm still stuck to no avail. This first thing I tried was simply using the filter I had and changing my math to use fixed point instead of floating point. However this was about 20 operations in series (multiplies, adds, subtracts, and one inverse, (( what's the most efficient way to do an inverse in the FPGA? ))) and the FPGA did not like that at all. So I tried to pipeline the operation. Now mind you this isn't a true pipline because new data cannot be introduced to the pipe in each cycle (I need the output of the last cycle before I can introduce new data,) but I was simply trying to split up the math and have the FPGA only do part of it on each iteration of the while loop, because I thought the FPGA would be able to run this filter way faster than I needed to.
Here's the error I'm getting...
Status: Compilation failed due to timing violations.
Click the Investigate Timing Violation button to display the Timing Violation Analysis window.
Device Utilization
Total Slices: 59.0% (12084 out of 20480)
Flip Flops: 28.5% (11692 out of 40960)
Total LUTs: 45.9% (18788 out of 40960)
Block RAMs: 0.0% (0 out of 40)
Timing
MiteClk (Used by non-diagram components): 33.04 MHz (69.24 MHz maximum)
40 MHz Onboard Clock: 40.41 MHz (30.29 MHz maximum)
Actual Xilinx Options
Synthesis Optimization Goal: Speed
Synthesis Optimization Effort: High
Map Overall Effort Level: High
Place and Route Overall Effort Level: High
Start Time: 6/6/2010 10:11:47 PM
End Time: 6/6/2010 10:57:33 PM
And then when I try to investigate the timing violations the "Timing Violation Investigator???" gives me this!!:
Possible reason(s):
An internal error occurred. Please try again or contact National Instruments.
Details:
Error Code --> -61499
Error Text --> <APPEND>
Additional Information: There is no matching tag in Xilinx twx file
There is no matching tag in Xilinx twx file
Also,
I was able to successfully run the "Timing Violation Investigator" a couple times. The first time it pointed to a multiply operation which i replaced with high throughput math and pipelined. The second time it pointed to "non-diagram components," how am I supposed to fix that?
I've attached the code and the xflow.log! Thanks for your time!
Thanks!
Ken
Attachments:
FPGA.zip ‏778 KB
xflow.txt ‏1138 KB

Hey Ken!
If you hit the "Investigate Timing Violation" button and go to the analysis page, it looks like there are a couple of math functions that are taking longer than expected.
If you replace them with high-throughput math equivalents (from the FPGA Math & Analysis palette) and manually configure the inputs and output FXP word/integer lengths, you might be able to get them within the timing requirements.
Let me know if that works!
Caleb Harris
National Instruments | Mechanical Engineer | http://www.ni.com/support

FPGA ERROR:HDLCompiler:806

Hi Guys,
I am having trouble compiling a piece of FPGA code that converts an array of four U8 numbers into a floating point number.
There are no labVIEW reported errors on the block diagram but when I attempt to compile (press the run button) I get the following error in the compilation status window.
LabVIEW FPGA: The compilation failed due to a xilinx error.
Details:
ERROR:HDLCompiler:806 - "C:/NIFPGA/jobs/SD41b8F_kGH6B4K/DeleteArrayNode_39.vhd"
Line 38: Syntax error near "/".
INFO:HDLCompiler:1061 - Parsing VHDL file
"C:/NIFPGA/jobs/SD41b8F_kGH6B4K/DiagramReset.vhd" into library work
I am compiling for a sbRIO-9606 and my operating system in Windows 7 64bit with LabVIEW 2011.
I found this post: http://digital.ni.com/public.nsf/allkb/2DA4F6A0C206E03A862578E9007DFECE that seems to refer to this problem being fixed for LV2011.
Please find my VI attached.
-Adam
Adam Amos | CPE Systems
[email protected]
Attachments:
To Float.vi ‏23 KB

Adam,
So the error has to do with the 3rd delete from array in your program as the result is a size 0 array. This is a known issue. Logically you could replace the 3rd delete from array with a wire and your code should compile and behave the same the since there are only 23 elements left in your array.
Kyle Hartley
RIO Product Support Engineer
National Instruments

FPGA Xilinx compilation failed. Access to the path 'C:\NIFPGA\corecache\activity.log' is denied.

I have just rceived my cRIO. I have installed all the necessary software and drivers and have written a VI in FPGA mode. However, when I try to compile the code I get the follow error message (see attachment). I have contacted NI support and they have been unable to solve this proble as of yet.
The NI engineer gave me the following advise:
1. Launch the Registry Editor by selecting Start » Run and then entering regedit in the Run window.
2. Press the Enter button to open the editor.
3. Find the following registry key in the path below:
HKEY_LOCAL_MACHINE\SOFTWARE\Wow6432Node\National Instruments\LabVIEW\11.0\AddOns\FPGA\CompilerPath_Xilinx12_4
* the Wow6432Node may not be correct in all cases. on my PC, you go to HKEY_LOCAL_MACHINE\SOFTWARE|National Instruments\LabVIEW\11.0\AddOns\FPGA\CompilerPath_Xilinx12_4
4. Under the Data Tab, you should see the path that your CompilerPath_Xilinx12_4 is linked to. Please confirm that it is linked to C:\NIFGPA\programs\Xilinx12_4
If you have Xilinx 11.5 installed, make sure it also is linked to the proper path.
5. If you have previous versions of LabVIEW installed, you will have to go to those versions as well. For Example if you have LabVIEW 2010 installed, please go to 10.0\AddOns\FPGA
Make sure that the CompilerPath_Xilinx12_4 or CompilerPath_Xilinx11_5 or CompilerPath_Xilinx10_1 are all correctly placed under the C drive as well as seen above in step 4.
6) Make sure that the "Working Directory" under LabVIEW 11.0 has the correct path of C:\NIFPGA\
7) After this, close otu the Registry Editor and navigate to where the FPGA Compile Worker is located. By default it should be here: C:\Program Files (x86)\National Instruments\FPGA\CompileWorker
8) In here open the "WorkerRootDirectory.txt" document and change the path. Make sure that it points to the C Drive.
9) Save and close the file. Restart your computer.
All of this was already correct and still cannot compile.
Solved!
Go to Solution.
Attachments:
FPGA.png ‏131 KB

Usually, an "Access to the path ... is denied." error stems from user permissions.
What Operating System are you using?
Are you using this tool from an administrative account?
Is there a custom security policy on your workstation that dictates user rights and permissions?
Is it possible to run LabVIEW as an administrator? (ex. in Windows 7, you would right-click on LabVIEW.exe and select "run as administrator.")
Best regards,
Matthew H.
Applications Engineer
National Instruments

How can I get 'sync' signals for sine wave out? [FPGA USB 7856R]

Hello,
I'm Sean Ahn using NI 7856R, USB FPGA with LabVIEW 2014.
I'm trying to make 'sync' signals for sine wave of adjustable frequency, like general function generator's sync out.
I use sine waves whose frequency is feedback-congtrolled between 25~30 kHz and need sync signals of square wave.
Like [1] below, when I try resettng two wavefom-generators, sine and sync signals are not perfectly synchronized.
And everytime I adjust sine's frequency, the phase difference between sine and sync changes arbitrarily
In case of [2] using 'zero-crossing detector', I have severe jitter of sync signals not suitable as 'sync' signals for other parts.
Please, give me some help.
Thanks in advance
Sean Ahn
[1] Reseting two waveform generators
[2] Zero-crossing detect

Here’s my issue. When I try to move any data between my PC and the iPad2 I receive an error message that states that “the [sync] session could not be started with the ipad, Please disconnect and reconnect the iPad and try again”
I have tried again and again by various methods etc . and all I get is the same message when I attempt to sync, backup or update the iPad.
I have tried the following AND FAILED:
Deselect all Apps, Music etc in iTunes, then attempt to sync
Disable and enable the iPad in device manager and restart itunes and try to sync again
Disable and enable Apple Mobile Device Services and sync/backup/update
Run iTunes as Administrator
Reboot all devices (iPad buy pressing two buttons at once)
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Connect directly to internet without a router
Tried to sync with all wireless turned off and in airplane mode
Running iTunes Diagnostics...... nothing all test passes
Changing USB ports and cables
Removing my SIM card and rebooting and trying to syc
Trying to sync via wifi only
Turning off all icloud services
Uninstalling all Apple Software and reinstalling again
I am syncing to a 64bit PC running Win 7 Premium with all the latest updates, all firewalls off. WiFi and direct connect ethernet to Internet service with and without router.
I am trying to Sync an iPAD 2 running iOS version 5.1.1 (9B206)
I am trying to update from iOS 5.11 to 6.01 by using Itunes 11.0.0.16.3 in a USB or directly through the iPad via wifi.
Please help as everything I have tried has failed.

FPGA for CAN, DI, AI help getting started

I am a new user to LabView.
I am trying to program the FPGA on a 9144 Ethercat chassis with modules 9423 (Digital input), 9201 (Analog input), 9853 (CAN). 9144 is connected to a cRIO-9024. There are more modules but if I can figure these out, the others should be almost the same.
I have tried to copy the code in the following examples but not all the referenced VI's are on my computer or there is problems with the code that I don't know how to fix
http://zone.ni.com/devzone/cda/tut/p/id/6628
http://zone.ni.com/devzone/cda/epd/p/id/5473
I am able to monitor the digital input and analog input using the real-time VI's, but that is pretty simple.
Normally, I would just pound away at it for a while until I got something that worked, except there are some deadlines that have to be met.
I need to be able to read and write CAN (this is to control a motor). The digital input needs to measure the frequency (Hz) of the incoming signal (count edges). Analog input I would assume would be the easiest as it is just reading a voltage. I realize that the only thing that really needs to run on the FPGA is the CAN. I believe (and hoping) that it is possible to have all the data input come through the FPGA so that the Real-Time VI's only deal with the usable values like Hz and then equate that to RPM for example. I am only looking to extract data at a rate of 1Hz.
If anyone could help me out with some basic code to get me started, I would appreciate it.

This FPGA VI has controls and indicators in it. It can only
run on the FPGA targets that support Interactive Front Panel Communication
(e.g. cRIO-9024) so that the host computer displays the FPGA VI front panel
window and the FPGA target executes the FPGA VI block diagram. Please refer to
LabVIEW Help (FPGA Module) for more information about the Interactive Front
Panel Communication.
However, support of Interactive Front Panel Communications
varies by FPGA target – NI 9144 is one of the targets that doesn’t support it. With
NI 9144, please use User-defined Variables to communicate between the host and
the NI 9144 FPGA target, and then your FPGA VI automatically runs when you
compile and download the FPGA VI to NI 9144 instead of clicking the Run button.
Here is a document about the data transferring between the FPGA and the host. Section User-Defined I/O Variables for Custom FPGA I/O Data describes how to use User-defined Variables.
Transferring Data between the FPGA and the Host (FPGA Module)
Here is more information for your reference:
1. Examples about programming FPGA on NI 9144:
<NI Example Finder> >> Hardware Input and Output >> NI-Industrial Communications >> EtherCAT >> FPGA Fundamentals
2. Help Topics:
<Start
Menu> >> All Programs >> National Instruments >> NI-Industrial Communications
for EtherCAT >> NI-IndCom for
EtherCAT Help >> Programming
the FPGA on NI 9144 Slave Device
Feilian (Vince) Shen

How do I create Filtered-X LMS (FXLMS) vi under FPGA project

Hi, Everyone
I am trying to implement FXLMS on cRIO FPGA.
I studied the buildi-in example: Adaptive Noise Control (cRIO).lvproj
There is a problem, I have no idea how to create "FXP Filtered-X LMS.vi" under a project
I know I can get typicall LMS by using:
Start IP generator >> LMS adaptive filter, and a pop-up window will show and help me to set the parameter.
But I don't know how to get FXP Filtered-X LMS.vi like the one in the proj.
Anyone knows?

First get the URL of your image. If you have not posted it yet, attach it as you did previously
post the reply then click on your attached link and copy the URL
quickly (5 minute limit on edits) return to your post and edit it.
When editing click the "insert an image" button
paste the image URL into dialog box.
submit edited post.
Again, thanks for sharing your findings!
Ben
Message Edited by Ben on 03-06-2008 10:29 AM
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction
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ROT button DE FPGA

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