RXRESETDONE is not asserted successfully

Question

I have question about RXRESETDONE is not asserted successfully .
Actually, it is never get asserted.
I am trying to use GTP tranciever on Artix-7 and I am using core from artix_gig_eth_pcs_pma_v11_5 to control GTP to use with 1G ethernet over fiber 1000baseX. I am running the last ISE 14.7, not Vivado
I found application notes which somewhat unspecific in addressing issue, also somehow it looks similar.
http://www.xilinx.com/support/answers/60488.html
Is it possible to get more info about it.
Also, there are production version of Artix-7which  needs special DRP sequence to fix issue at reset of GTP.
http://www.xilinx.com/support/answers/53561.html
and in data sheets.
http://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf
However, sequence described in data sheets:
When I use Chipscope to observe this sequence it is not behave as expected.
In this sequence RXPMARESETDONE going down two time. First time it is going after GTRXRESET asserted
But in my case it never go down the second times and from description it is not clear what will bring this signal done for proper implementation of core sequence of restoring bit 11 througn DRP write.
In summary I see two things which are wrong: RXRESETDONE is never asserted, and it could be related but RXPMARESETDONE never go down the second time and as result correct sequence never get execurted.
In reality 2ms timeout reissue reset every 2ms and tranciver never comeout in proper state.
Does anybody has good suggestion on how to deal with issue or at least to have the better understanding of what is going on. Alsois it possible to explain needs for DRP correction at startup/reset. Some other people I talked did not implement DRP correction and have GTP working also for different application (not 1G ethernet)
Any information will be helpful
Thank you, Leonid
 

Answer 1

In the first try I used the RXCDR_CFG from ug484 Table 4-14:
//    assign cdr_cfg_gen1 = 83'h0_0000_47FE_1060_2450_1010;
//    assign cdr_cfg_gen2 = 83'h0_0000_47FE_2060_2450_1010;
//    assign cdr_cfg_gen3 = 83'h0_0000_87FE_2060_2448_1010;
I also did try the new settings from AR# 51369
// from Xilinx AR# 51369:
    assign cdr_cfg_gen1 = 83'h0_0000_47FE_1060_2448_1010;
    assign cdr_cfg_gen2 = 83'h0_0000_47FE_2060_2448_1010;
    assign cdr_cfg_gen3 = 83'h0_0000_87FE_2060_2444_1010;
None of them work with SSDs / HDDs which use SSC. (SATA Gen1 and Gen2, I dont use Gen3 yet.)
Is there any other parameter which influences the CDR with SSC? What about the CDR_HOLD pin?
Thanks for your reply.