Several VHDL Modules in One Test Bench

Question

I am working with a image system consisting of three major parts:
- A CCD array
- A FPGA card
- A frame grabber
I have written one VHDL module for every component and now I would like to simulate them in one test bench. Is it possible to include several modules in one test bench? Or do I need to instantiate two of them as components?
Thanks in advance!

Answer 1

johnju wrote:
I am working with a image system consisting of three major parts:
- A CCD array
- A FPGA card
- A frame grabber
I have written one VHDL module for every component and now I would like to simulate them in one test bench. Is it possible to include several modules in one test bench? Or do I need to instantiate two of them as components?
You certainly can simulate an entire system. There is no reason why you cannot.
I generally create system simulation test benches which have the FPGA as just one component. So in your case, you'd model the CCD, find or write models for the converters, wire them to the FPGA, and then write models for the transport between the FPGA and the frame grabber card, and finally finally you will have to write a model of the frame grabber as a data sink.
It can be a lot of work, but if you want to prove out your system, and also exercise the FPGA with real stimulus, this is the way to go.
And if you feel the need to do a post-place-and-route timing simulation, if you are clever and use VHDL configurations, you can simply swap the timing model for the FPGA source in the test bench's instantiation of the DUT.