Verilog test bench error -- all vcd dumpvars must be executed at the same simulation time

Hi Folks,
I have ISim version 13.1.
During simulation of a large module with many sub modules and instances, I want to be able to dump objects to a .vcd file.
However when I use the construct
@$dumpvars (0, module_name.sub_module_Name.signal_name);
where these names are known within the test bench, I get an error message:
error: Instance: /module_name/: All vcd dumpvars must be executed at same simulation time.
I do not understand what that means and what to do about it.
Can some one help ?
By the way, when I eliminate the signal_name in the above construct, all signals do get dumped to the .vcd file...
I did not enclose the source code as it is too large...

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I run weblogic's example MedRec as a cluster. I follow the
instruction and it works.
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Verilog test bench error -- all vcd dumpvars must be executed at the same simulation time

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