Simulator doesn't match disk created for menus

Hi,
I have created a multimenu, 2 track DVD. I have set all the menu connections in the tracks to go back to the menu button that corresponds to the marker on the track. This works fine in the simulator and all the menu button pushes go back to the correct menu buttons. However, when I build the project and use DVD player to view it, pushing the menu button for track 1 always takes me back to the Chapters 1-6 menu I have created and it always highlights button 1 to matter where I am in track 1. I tried this over and over after deleting preferences, reinstalling DVD studio, restarting and I always get the same result. Is there something else I can try? Is there anyway to examine the build results to see where the error may be? Is there anyway to correct the build results?
Thanks

Welcome to the discussions...
Just to be clear, you have set a different menu call on each chapter marker so that when the track is played, pressing the 'menu' button should take the viewer to the menu which holds the button for that particular chapter marker, regardless of where they started playback from? So in effect they could start from menu 1, watch a bit of the track and then go to menu 5 if they are at a marker late in the track?
This should work and I would urge you to check your connections in the connections tab. The alternative is to make a simple script and point the menu call at it instead. If I assume that you have got five buttons per menu that play a marker, and four menus (so 20 markers in total), the script is this:
mov GPRM0, SPRM7
goto 6 if GPRM0 >5
goto 8 if GPRM0 >10
goto 10 if GPRM0 >15
Jump Menu1 \[GPRM0\]
Sub GPRM0, 5
Jump Menu2 \[GPRM0\]
Sub GPRM0, 10
Jump Menu3 \[GPRM0\]
Sub GPRM0, 15
Jump Menu4 \[GPRM0\]
So if you are on a marker 1 through to five, line five jumps you to the first menu. Otherwise line 6 (markers 6 through to 10) takes you to menu 2. Line 8 (markers 11 through to 15) go to menu 3 and beyond marker 15 you go to line 10, and thus menu 4.
The square brackets are GPRM based button jumps, meaning you will land on the button with the number value the same as the marker on that menu. To make sure that the marker values equal the button values (i.e. 1 through to 5 on each menu) I've subtracted a value accordingly each time.
The scripted solution is probably overkill, but will work reliably. You should check your connection settings first, and remember that the simulator is NOT a good indication of what will actually happen, only an approximation.
Good luck!

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input async;
input clk;
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reg [1:3] resync = 3'b000;
reg counter = 1'b0; //keeping track of which edge of async we're on
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end
//^^I'm pretty sure this makes the 'switch' register switch very quickly when 'async' changes
//I've included this always block because I wanted to sync my input signal to the clock, because I read that FPGAs don't do well with asynchronous stuff
always @ (posedge switch)
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NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50 %;
NET "switch" TNM_NET = "switch";
TIMESPEC TS_switch = PERIOD "switch" TS_clk HIGH 50 %;
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INST "clk_BUFGP" LOC = F1;
NET "clk" LOC = F1;
NET "o" SLEW = FAST;
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Other details: using a Xilinx XEM 6001 FPGA, and ISE Design Suite 14.4 The way I've tested is to hook up a function generator to pin A2 and a oscilloscope to pin C1, and all I see is noise. Is there any obvious problem here, maybe something like I am not actually connecting to the physical pins properly or something?

There are several things wrong for your code to synthesize properly, but I would still expect that your "o" output would toggle at one edge of the input signal if your clock is really running, and your async input from the signal generator is driving the correct logic levels. I would try a couple tests to make sure this isn't a hardware issue:
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2) Build a counter that counts up on evey posedge of clk and run its MSB to the "o" output. See if this toggles at the expected frequency. This will show if your clock input is really hooked up correctly and running.
Errors in the code:
switch <= resync[2] & !resync[3];
switch <= resync[3] & !resync[2];
These two lines run in parallel, so switch will really only sense one edge of the input signal. That's because the second assignment statement "wins" over the first, so it's the same as just writing:
switch <= resync[3] & !resync[2];
If you really wanted to detect both edges, you could OR the two conditions together like:
switch <= resync[2] & !resync[3] | resync[3] & !resync[2];
You could also do this using "if" statements like:
if (resync[2] & !resync[3]) switch = 1;
else if (resync[3] & !resync[2]) switch = 1;
else switch = 0;
There are probably other ways to do this.
Then in the second process you use "switch" as a clock, which is a bad practice. It's better to use
it as a clock enable like:
always @ (posedge clk)
if (switch)
begin
end
Finally those time delays are ignored for synthesis, so these lines:
#t1 o <= ~o;
#t2 o <= ~o;
are the same as:
o <= ~o;
o <= ~o;
and again, they happen in parallel (non-blocking assignments), so it's the same as
o <= ~o;
Which is why I would assume the output would toggle once per input async period. If you don't see that you need to verify your connections.

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