FPGA simulation doesn't match actual performance

Question

I am trying to write a verilog code that will trigger on the positive edge and negative edge of an input signal (which I've called 'async'). My desired output is a short blip (when compared to the frequency of async) on each edge of async, which is slightly delayed from the edge ('t1' and 't3') and whose duration can be controlled ('t2' and 't4'). The comments say what I think my code is doing, but I am new to Verilog, and don't really understand anything. Any help is appreciated.
Here is my code:
`timescale 1ns / 1ps
module attempt5(async, clk, o);
input async;
input clk;
reg switch = 1'b0; //will tell me when async changes
reg [1:3] resync = 3'b000;
reg counter = 1'b0; //keeping track of which edge of async we're on
output reg o = 1'b0;
parameter t1 = 0;
parameter t2 = 100000000;
parameter t3 = 0;
parameter t4 = 100000000;
always @ (posedge clk)
begin
switch <= resync[2] & !resync[3];
switch <= resync[3] & !resync[2];
resync <= {async, resync[1:2]};
end
//^^I'm pretty sure this makes the 'switch' register switch very quickly when 'async' changes
//I've included this always block because I wanted to sync my input signal to the clock, because I read that FPGAs don't do well with asynchronous stuff
always @ (posedge switch)
if (counter == 1) begin
counter = 0;
#t1 o <= ~o;
#t2 o <= ~o;
end else begin
counter = 1;
#t3 o <= ~o;
#t4 o <= ~o;
end
//^^ When the 'switch' register changes, start the the short blip
endmodule
and my constraints file:
NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50 %;
NET "switch" TNM_NET = "switch";
TIMESPEC TS_switch = PERIOD "switch" TS_clk HIGH 50 %;
NET "async" LOC = A2;
NET "o" LOC = C1;
INST "clk_BUFGP" LOC = F1;
NET "clk" LOC = F1;
NET "o" SLEW = FAST;
The code works in the synthesizer, but when I try to test the code using a 1 Hz square wave for the "async" signal and monitoring the "o" using a oscilloscope, nothing happens.
Other details: using a Xilinx XEM 6001 FPGA, and ISE Design Suite 14.4 The way I've tested is to hook up a function generator to pin A2 and a oscilloscope to pin C1, and all I see is noise. Is there any obvious problem here, maybe something like I am not actually connecting to the physical pins properly or something?

Answer 1

There are several things wrong for your code to synthesize properly, but I would still expect that your "o" output would toggle at one edge of the input signal if your clock is really running, and your async input from the signal generator is driving the correct logic levels.  I would try a couple tests to make sure this isn't a hardware issue:
1) Change "o" to simply follow the async input.  This will verify that your input and output pins are correct and your input waveform has good logic levels.
2) Build a counter that counts up on evey posedge of clk and run its MSB to the "o" output.  See if this toggles at the expected frequency.  This will show if your clock input is really hooked up correctly and running.
Errors in the code:
switch <= resync[2] & !resync[3];
switch <= resync[3] & !resync[2];
These two lines run in parallel, so switch will really only sense one edge of the input signal.  That's because the second assignment statement "wins" over the first, so it's the same as just writing:
switch <= resync[3] & !resync[2];
If you really wanted to detect both edges, you could OR the two conditions together like:
switch <= resync[2] & !resync[3] | resync[3] & !resync[2];
You could also do this using "if" statements like:
if (resync[2] & !resync[3]) switch = 1;
else if (resync[3] & !resync[2]) switch = 1;
else switch = 0;
There are probably other ways to do this.
Then in the second process you use "switch" as a clock, which is a bad practice.  It's better to use
it as a clock enable like:
always @ (posedge clk)
  if (switch)
    begin
    end
Finally those time delays are ignored for synthesis, so these lines:
#t1 o <= ~o;
#t2 o <= ~o;
are the same as:
o <= ~o;
o <= ~o;
and again, they happen in parallel (non-blocking assignments), so it's the same as
o <= ~o;
Which is why I would assume the output would toggle once per input async period.  If you don't see that you need to verify your connections.