Sysgen : How to read the input port data type, width and rate dynamically in a masked subsystem ?

Question

Hello everybody,
     I am designing a general purpose block in system generator. I pass the user parameters to the block through masking it. Some user parameters can change the block configuration. The input port data type, width and rate can also affect the block configuration.
     The problem is that these values (input port data type, width and rate) are subject to change. So I should read them dynamically, then change the block configuration through programming the "Initialization Commands" field. But unfortunately there is no straight way to read the input port information.
     There are some methods in for example the "Black Box". these are:
input_width = this_block.port('din').width;
input_rate = this_block.port('din').rate;
But these methods are not applicable to a masked subsystem.
I have tried other ways also. You can find them below. None of them worked.
Does anybody know how can I solve this problem?
Other ways I tried:
1)
design_name([],[],[],'compile')                                       
q=get_param(gcb,'PortHandles');
get_param(q.Inport,'CompiledPortDataType')
get_param(q.Inport,'CompiledPortWidth')
get_param(q.Inport,'CompiledPortDimensions')
design_name([],[],[],'term')
2)
ssGetInputPortDataType
3)
ts = Simulink.Block.getSampleTimes([gcb '/Input'])
 

Answer 1

Today we rely on Simulink to perform parameterization of your designs in two ways:
Parameterizable Subsystems and Blocks : Parameters themselves can be MATLAB expressions that need to be evaluated for which we need the MATLAB interpreter
The very useful Rate and Type propagation or Simulink compilation that allows us to specify types & rates in one location that gets systematically propagated to all.
To truly make the HDL Netlist that is generated from SysGen parameterizable, we would have to implement some of this capability in the HDL netlist itself by:
Using Generics(VHDL) or Parameters(Verilog) - We would have to capture the bit width(type) propagation through levels of hierarchies and finally parameterize the IP itself based on this value
Since IP itself does not have this capability through generics, we would have to package a separate tcl script that updates the IP parameterization appropriately in response to top level parameters(or GUI parameters)
Interpreting MATLAB expressions and translating them into VHDL/Verilog expressions (alternatively tcl expressions of IP). In simulink, mask parameters can be passed from one level to the next. Also parameterization of a block can be composed of Matlab expressions using variables from ancestor masks & the MATLAB interpreter – so we will need to somehow capture that as well.