The critical path is generated by BUFGCTRL, how can i constraint it?

Question

Hi expert:
       The critical path as below, can i set flash path?If not , how can i do?
//---------- Select PCLK -------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel <= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_reg2)
pclk_sel <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_reg2))
pclk_sel <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel <= pclk_sel;
end
end
pclk_slave_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_slave
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel_slave),
.S1 ( pclk_sel_slave),
//---------- Output --------------------------------
.O (CLK_PCLK_SLAVE)

Answer 1

Hi,
Yes you can apply false path constraint on that path as the startpoint and endpoint seem to be valid.
(note-for BUFGCTRL you cant apply ignore constriant on path reaching the CE pin --refer to datasheet)
For syntax refer:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug903-vivado-using-constraints.pdf
Thanks,
Rajesh
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