Trace to Pads Net Group Options not Avalible

Question

Hello,  To explain my problem I have prepared as
easy example as it is possible.
Let suppose
that we have a circuit diagram that is shown below in the attached figure
(Figure A). As can be seen the circuit diagram consists of three resistors R1,
R2, R3 and one connector J1. These parts are connected each other by three nets
1,2 and 3. Nets 1 and 2 is grouped into HV group with a Multisim clearance
option (to trace, to pads, to copper parts) equal to 10 mil. In Ultiboard this
HV group in Net Group Tab is set to clearance option (to trace, to pads, to
copper parts) equal to 100. It results from the fact that both lines (1,2)
exhibit, in example 1000V, while net 3 only 10V. Thus these nets, namely 1 and
2 posses internal clearance 10 mil to each other and external 100 mil with
respect to the net 3. Up to now everything works fine but when we turn on the
Autorouting option for a given geometry configuration (Figure B) it will
produce complete disaster (Figure C). As can be seen in figure C), the
Autorouter does not take into account the “Group HV” clearance to the pads. The
green trace from Resistor R1 to connector J1 should look more likely like in
Figure D.
My question
is: Why the Ultiboard does not take into account the Group HV clearance to the
pads. ??????
I was
trying to solve this problem in many different ways.
In example,
I have changed manually the pad clearance of a connector J1 to a given value.
It works – the Autorouter will produce the result that looks like in figure D),
but it will produce the clearance to each net independently of a net group that
it belongs !!!!!.
In the J1 part pad clearance option one can set
“Use net settings” – but it will produce only 10 mil clearance for pads. Why
there are no option “Use Net Group settings” ????????? I mean that a clearance
of a pad is different for different groups or nets !!!!!!!

Answer 1

Hello, it’s
me once again.
I have
already made a lot of tests with different examples and I have the following
ideas, solutions and propositions:
1)     
The
main algorithm “engine” of the software does not work properly, namely during
the operation the algorithm does not take into account the clearance properties
of a net that is currently under construction. The engine takes only the
clearance properties of a nets/vias/pads which are approached during the engine
operation. This result in substantial amount of mistakes in “Follow-me”-tool
and Autorouter.
Possible solutions: Actually, there are no easy
solutions - I am working on it and I am trying to elaborate procedure that may
helps.
2)     
The
main idea of software is also not perfect. In principle, THT/SMD pads and vias
should do not exhibit own clearance properties if they are already connected
via nets. If a net exhibit 1500 Volts (clearance = 200 mil) then the THT-pad
should at lest exhibits the same clearance property.  In Ultiboard it is set to 10 mils for each pad. This may results
in substantial amount of mistakes in “DRC check rule”
Possible solutions: One can manually change the
clearance properties of a pads/vias. But this is not good solution especially
if there exists a lot of parts with different pads configurations and different
nets connection configuration (It takes a lot of time to carry it out
precisely). Moreover it does not help if in our design there are different Net
groups. There are not “Use net Group” option thus pad/vias exhibit the same
clearance property for ever and with respect to all others nets independently
of the group that they belongs.
Above mentioned problems are crucial in high
voltage electronics (staring from 115V). Thus NI Design suite is not suitable
for this type constructions (power supplies). It works properly with certain
conditions, i.e. with low voltages.