Two sessions are blocked each other in

Hi All,
My database is Exadata machine. 11.2
These days we encountered one case, that is two sessions are always blocked by each other. I get this info from v$session blocking_session.
For examle, the information looks like
sid blocking_session event
1 2 libarary cache lock
2 1 row cache lock
and as you know there are many other sessions are blocked by sid 1.
By lookiing up v$sql, I got the sql for these 2 sessions.
/* QSMQ VALIDATION */ ALTER SUMMARY "XXXXX"."Gxxx_CP_CAL_TIME_TEMP_MV" COMPILE
/* QSMQ VALIDATION */ ALTER SUMMARY "XXXXX"."Gxxx_CP_CAL_TIME_MV" COMPILE
Both of these 2 MV share some underlying objects. And both of the 2 sessions started at the same time roughly.
If the compilation incurs the lock on the object, why the 2 sessions block each other?
Can someone give me some tips,please?
Best regards,
Leon

Leon,
sid blocking_session event
1 2 libarary cache lock
2 1 row cache lockYou are saying that above situation does not cause a deadlock error to be generated in either one of those two sessions?
/* QSMQ VALIDATION */ ALTER SUMMARY "XXXXX"."Gxxx_CP_CAL_TIME_TEMP_MV" COMPILE
/* QSMQ VALIDATION */ ALTER SUMMARY "XXXXX"."Gxxx_CP_CAL_TIME_MV" COMPILEThese to me look like programmed 'ALTER SUMMARY' commands (the comment in front of the statement seems to indicate so). It's the application that's doing this right?
- Can you reproduce this with two sqlplus sessions?
- Why is the application compiling the MV's? Are underlying objects being altered frequently?
- Should the application not just be 'refreshing' the MV's instead of compiling them?
Just some thoughts.
Toon
Edit:
Dom's right. The alter summary statements seem to be Oracle internal calls generated by DBMS_MVIEW.REFRESH executions.
Edited by: Toon Koppelaars on Nov 24, 2011 10:41 AM

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Please see my VI attached or the given screenshot.
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Attachments:
FPGA Loop Rate.PNG ‏72 KB
FPGA Main.vi ‏251 KB

Hi, thanks so far.
Originally the control was inside the loop. Then I tried if it makes a difference if it's outside.
Ok, i really seems to be that default value of "100000" for "AO Update Period".
Starting the VI directly woks like expected. Having "AO Update period" inside the loop makes it possible to control it as it's running.
But, please see the attachment. When starting the FPGA through RT and setting the appropiate value, it does not seem to work. The oscilloscope show's the same behavior like "AO Update Period" was 100000.
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Having changed the default value to 10 works so far, but I am not able to changed it (see attachment).
So the problem is: Why is "Read/Write control" not working here? Why is still the default value used?
Attachments:
FPGA Loop Rate 2.PNG ‏5 KB

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Two sessions are blocked each other in

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