Value not detected on clk edge

Question

I am using vivado 2015.1.
My piece of FSM code is
always @(posedge aclk or negedge aresetn)
    begin
        if (~aresetn)
            wr_current_state                    <= WAIT_INIT_DONE;
        else
            wr_current_state                    <= wr_next_state;
    end 
// states of my concern for this question
`WAIT_AWREADY:
begin
if (axi_wready)
begin
axi_wvalid = 1'b1;
wr_next_state = WAIT_FIFO_DATA;
end
else
begin
axi_wvalid = 1'b1;
wr_next_state = WAIT_AWREADY;
end
end
`WAIT_FIFO_DATA&colon;
begin
some code
end
In the simulation figure attached,  we can see clearly that  when current state = WAIT_AWREADY ,   axi_wready = 1. Hence FSM should move to next state in next cycle. But simulation is showing that FSM was in WAIT_AWREADY state for 2 cycles. Can anyone tell me why is this behaviour in simulation?

Answer 1

HI 
please note that FSM is written for changing wr_next_state. (as it should be).
And "wr_current_state" value changes only a clock cycle after the "wr_next_state" value  changes.
If my guess is correct,In the simulation window, the "statename[127:0]"  must have been mapped to "wr_current_state"  and hence the two cycle delay.  (as expected)
If your intention is to monitor FSM transitions accurately, you should looking at "wr_next_state" in the simulation.