Vivado simulation - block memory module failure

Question

Hi,
I'm simulating a project with my own IPs. one of the IPs has a block memory generator (8.2).
The simulation stops after 35 ns and tck message:
Block Memory Generator module TOP030815.design_1_i.golgol_0.U0.blk_mem_gen_GOLAY_inst.inst.native_mem_module.blk_mem_gen_v8_2_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
Failure: ERROR:add_1 must be in range [-1,DEPTH-1]
Time: 35 ns Iteration: 2
$finish called at time : 35 ns : File "../../../project_1.srcs/sources_1/ipshared/ornim.medical/golgol_v1_0/a6138b30/hdl/golgol_v1_0.vhd" Line 93
xsim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:34 . Memory (MB): peak = 980.820 ; gain = 37.723
INFO: [USF-XSim-96] XSim completed. Design snapshot 'TOP030815_behav' loaded.
what is the problem? 
Thanks,
Danna

Answer 1

Did you use the AXI4 interface for the block memory generator IP?
This kind of failure is typically seen when master and slave AXI are not initialized. e.g. when the slave TVALID and TDATA are in an 'U' or 'X' state.
You need to firstly examine the testbench (or the AXI bus drivers) and ensure they're all initialized.
For instance,
  -- Data slave channel signals
  signal s_axis_data_tvalid              : std_logic := '0';  -- payload is valid
  signal s_axis_data_tready              : std_logic := '1';  -- slave is ready
  signal s_axis_data_tdata               : std_logic_vector(15 downto 0) := (others => '0');  -- data payload
  -- Data master channel signals
  signal m_axis_data_tvalid              : std_logic := '0';  -- payload is valid
  signal m_axis_data_tdata               : std_logic_vector(23 downto 0) := (others => '0');  -- data payload