Simulation error : size mismatch in mixed language port association with VIVADO simulator

Question

Hi,
I have instantiated a VHDL module in  a verilog top file . When I tried to simulate the verilog top , I received the following error .
ERROR : Size mismatch in mixed language port association , vhdl port  vid_data
(Simulation tool : VIVADO simulator . VIVADO ver : 2015.1)
// Following is the instantiation of  VHDL module in verilog top file
VPS  VPS_inst 
     .clk (VPS_clk),
     .reset_n(~user_reset),
     .vid_active_video(data_valid),
     .vid_data(data_to_mem)
The port 'vid_data' is declared in the VHDL module as std_logic_vector (15 downto 0)
"vid_data   : out std_logic_vector(15 downto 0)"
'data_to_mem' is declared in verilog top file as  "wire  [15:0]   data_to_mem" . 
No size mismatch exists actually . But , I am getting the above mentioned error in simulation.
I have searched for similar threads . Nothing was useful . 
Does anyone know how to solve this?
Thanks and Regards
Raisa
 

Answer 1

You might also get this error if you mis-spelled "data_to_mem" such that the declaration did not match the instantiation port map.  For example:
wire  [15:0] data__to_mem;  // double underscore before "to"
VPS  VPS_inst 
     .clk (VPS_clk),
     .reset_n(~user_reset),
     .vid_active_video(data_valid),
     .vid_data(data_to_mem)  // only one underscore before "to"
In Verilog this is not an error unless you disable automatic net inference.  In this case Verilog is happy to create a single wire for data_to_mem, but then you would be trying to attach a 1-bit wire to a 16-bit port.  That would also be valid in Verilog, but not allowed for connections to VHDL.
I typically avoid this sort of error by placing:
`default_nettype none
at the top of each Verilog file, and
`default_nettype wire
at the bottom of each Verilog file.  This prevents the automatic creation of wires when you mis-spell or forget to declare nets.