Zc706 board with PCIe and SFP with tandem boot

I am trying to add gigabit ethernet via SFP (ala xapp1082) to the zc706 pcie trd reference design and I get the DRC error:
[Drc 23-20] Rule violation (HDTC-6) Non-stage-one logic illegally placed - Non-stage-one logic 'z7_pcie_trd_i/gig_ethernet_pcs_pma_0/inst/pcs_pma_block_i/transceiver_inst/gtwizard_inst/inst/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i' is placed at site 'GTXE2_CHANNEL_X0Y10' inside stage one Pblock 'z7_pcie_trd_pcie_7x_0_0_main_pblock_boot'. Non-stage-one logic should not be placed inside a stage one region.
Which I take to understand that the gigabit transfer for the SFP is in the tandem stage 1 boot area (the small .bit file just for enumerating the pcie port) and it needs to be in the stage 2 area. Can it be moved to stage 2 and if so how? Or can that DRC error be suppressed safely?
Thanks,
Clark

yes you do that in the XDC files. Give the Location constratints for the GT which you want to lock. IF you are using the SFP, then the GT locations are primiary fixed based on the locations of the SFP's. You can check those locations from the ZC706 user guide. You can give pin locations to these for the GT TX, RX outputs which will automatically lock the GT hard blocks as required.

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I received MSI board from RMA, and it doesn't boot

I recently RMA'd a board the name of it is msi k9n6pgm2-v2, and I got it back in this condition.
I was wondering, what I should do about it.

Quote from: Panther57 on 01-September-12, 08:27:39
>>Posting Guide<<(added this for you Panther)
Sounds to me, that if you just RMA'd the board and got it back not working... the guarantee the fix, right? Also when you do an RMA, it is very likely that we/you can get sent an already ready to go board of the same. That makes turnaround quicker and the things you show in the picture, might be from previous owner(s). You have pictures.. but explaining is limited.. top picture..dirty/scratched? The lower picture.. The, not all the way around solder? The screw Head should make 360 contact.. it looks like all will be OK, when mounted? You can always solder the full ring. Make sure it is meant to be fully bridged... again the screw head looks like it will contact all.
You didn't say, why you sent it in, what was wrong with it, to be fixed? If it was no boot... let them know. Is it your board? Can the no boot be Bios Settings... another reason? Boot order and a Memory Stick plugged in, can make your PC think it's to use the Mem Stick for boot and not the HDD. Possibly it memory... it's usually the first culprit.
If you read the posting guide.. it will explain why we ask for equipment information. Look at the bottom of my post. If we have an equipment list and more knowledge about your no boot.. we can help better. Welcome
Good Luck
I sent it in because, it would only boot if memory was in DIMM1, I had tried different sticks of DDR2 memory, in different configurations. I should have said, that I couldn't get it to POST. Also, the memory had been tested in different computers.

Need help to interface InRevium's TB-FMCH-HDMI4K Board with ZC706 Eval board

We (PathPartner Technology Consulting Services) have recently procured the above-mentioned card(from Inrevium) for supporting HDMI display (HDMI2.0 for 4K) for our FPGA-based Video Codec solution.
We are implementing this solution on ZC706 board (Zynq-7045 based)
We did get access to reference designs from Xilinx’s HDMI Reference Design lounge wherein the Reference design is targeted for KC705 evaluation board. It seemed feasible to implement the same design on ZC706 board since both the devices in KC705 and ZC706 use the same XCVR.
While implementing the design on ZC706 board, we could not generate bitfiles due to DRC violations. We did set the pin assignments made in XDC file targetting ZC706 (compared to KC705).
The DRC errors are:
[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed. The problem bus(es) and/or net(s) are IPI_INST/hdmi_ipi_i/hdmi_gt_0/inst/drurefclk_to_qpll.
[DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 2 out of 49 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DRU_CLK_P_IN, DRU_CLK_N_IN.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
Delving further:
The HDMI 2.0 Design requires GT differential clock pairs for 3 of its clocks, the pins are as mentioned below:
In the reference design that is based on the KC705 board, these pins are connected to the approriate GT Differential clock pairs as below:
set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN] (FMC_HPC_GBTCLK0_M2C_P on KC705)
set_property PACKAGE_PIN G8[get_ports DRU_CLK_P_IN] (SMA_MGT_REFCLK_P on KC705)
set_property PACKAGE_PIN E8 [get_ports TX_REFCLK_P_IN] (FMC_HPC_GBTCLK1_M2C_P on KC705)
But in case of ZC706 we could find only 2 GT pairs: FMC_HPC_GBTCLK0_M2C and FMC_HPC_GBTCLK1_M2C that corresponds to pins AD10 and AA8 respectively.
We could not find another differential clock pin on HPC connector with similar properties for DRU_CLK_P_IN.
We have set the constraints as follows:
set_property PACKAGE_PIN AD10 [get_ports HDMI_RX_CLK_P_IN]
set_property PACKAGE_PIN AA8 [get_ports TX_REFCLK_P_IN]
and
set_property PACKAGE_PIN AF10 [get_ports DRU_CLK_P_IN]: Need to find an appropriate pin on ZC706 board
Please refer to the attached .xdc file that we are using for the bit file generation on ZC706 board (we have retained the file name similar to one used for KC705 in the reference design).
It will help us if we can find an alternative pin for the DRU_CLK_P_IN on ZCZ706 board
Another alternative would be: We do not need the RX port. Hence, if RX can be completely disabled, the RX CLK pin can be used for DRU_CLK_P_IN. Need to know how RX can be disabled.
Looking forward for guidance in resolving the above-mentioned...
Thanks and Regards
Lalith

Hi Satish,
For the TB-FMCH-HDMI4K Card that we have procured from InRevium, we have got a reference design that is targetted for KC705 board. We have a ZC706 board and intend to get this card operational on ZC706. It seemed feasible since both the devices in KC705 and ZC706 use the same XCVR.
The HDMI 2.0 Design requires GT differential clock pairs for 3 of its clocks, the pins are as mentioned below:
In the reference design that is based on the KC705 board, these pins are connected to the approriate GT Differential clock pairs as below:
set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN] (FMC_HPC_GBTCLK0_M2C_P on KC705)
set_property PACKAGE_PIN G8[get_ports DRU_CLK_P_IN] (SMA_MGT_REFCLK_P on KC705)
set_property PACKAGE_PIN E8 [get_ports TX_REFCLK_P_IN] (FMC_HPC_GBTCLK1_M2C_P on KC705)
But in case of ZC706 we could find only 2 GT pairs: FMC_HPC_GBTCLK0_M2C and FMC_HPC_GBTCLK1_M2C that corresponds to pins AD10 and AA8 respectively.
We could not find another differential clock pin on HPC connector with similar properties for DRU_CLK_P_IN.
We have set the constraints as follows:
set_property PACKAGE_PIN AD10 [get_ports HDMI_RX_CLK_P_IN]
set_property PACKAGE_PIN AA8 [get_ports TX_REFCLK_P_IN]
and
set_property PACKAGE_PIN AF10 [get_ports DRU_CLK_P_IN]: Need to find an appropriate pin on ZC706 board
Please refer to the attached .xdc file that we are using for the bit file generation.
It will help us if we can find an alternative pin for the DRU_CLK_P_IN on ZCZ706 board
Another alternative would be: We do not need the RX port. Hence, if RX can be completely disabled, the RX CLK pin can be used for DRU_CLK_P_IN. Need to know how RX can be disabled.
Looking forward for your guidance in resolving the same
Thanks and Regards
Lalith

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What_happen_now.doc ‏25 KB
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Quote
So, my question is, since every other MB manufacturer seems to have figured out how to support both IB and SB chips on z68 systems why hasn't MSI? Is this support forthcoming or do I need to invest in a new MB or a new CPU just to be able to OC again?
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LV acquire the print information from the embed board with Linux system through serial port

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Is the Nexys2 board (with spartan 3e FPGA) compatible with the FPGA module

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I have an almost 2 years old iBook G4 14" 1.2GHz. Or better said - had. The logic board died some weeks ago.
My main point here is to find out if I can replace the faulty Logic Board with something faster, i.e. 1.33 or 1.42 GHz. I have heard some rummours that the cooling systems are a bit different and I am affraid that a faster Logic Board won't fit.
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Well, that's exactly what I thought first, but we are talking about an iBook here. That meens, that the 'video card' is actually only a chip soldered on the logic board and the fan turns on only when the computer has reached around 65-70°C.
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I hope that we can resolve this issue.

Zc706 board with PCIe and SFP with tandem boot

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