Zynq 7000 performance

Question

The Zynq 7000 used in the newly announced cRIO-9068 has me interested.
Especially the statement: "The processor and FPGA fabric communicate over 10,000 internal interconnect, delivering a performance between a microprocessor and FPGA fabric that is physically impossible to accomplish between a discrete processor and an FPGA implemented on a printed circuit board."
Something I've been wondering for a while is if this tight coupling of ARM cores and FPGA speeds up DMA Transfers between "host" and "target".  I have seen on a PXIE 8115 coupled with a Flex RIO 7895 a minimum latency of around 6 microseconds per single DMA transfer, making transfers of small amounts of data relatively time consuming (Meaning that a transfer of 1 element or 100 elements costs about the same amount of time).
Is this latency lower in the new design?
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant

Answer 1

Hi Colden,
thanks for the interesting reply.  One thing I don't understand is how Interrupts help transfer data (I thought they were the FPGA-RT version of occurrences).  In fact the help for the "Wait on IRQ" on the RT side states that the function will actually hog a CPU and may cause other code to stop executing until it has finished executing.  This is certainly something I want to avoid.
I should perhaps clarify a bit more what I'm referring to.  I should really be using the word "Overhead" instead of "Latency" when referring to the DMA calls.  Where our control loop is spending significant portions of time waiting for data from the FPGA, this kind of amounts to the same thing but it's not strictly the same.  If we wait 6 us for data arriving and anohter 6us before it can be sent (Because this is the overhead associated with the SMA transfer) then we have 12 us delay if we simply loop data back and forth between the FPGA and RT.
I have benchmarked DMA FIFOs on a PXIe-8115 with a 7865R and have found that the minumum transfer time for a single DMA is around 6us (According to RETT).  This is for sending a single U8 over DMA.  For approximately 100 U8s we still need the same time of approximately 6us.  Only over 100 U8s do we start to see a linear increase in DMA transfer execution time (0f 60ns per element IIRC).  What this means is that the transfer of data over DMA is only really efficient when we are sending at least 100 elements.  In our application we send less that that, so we're essentially in the region where the DMAs are not operating at full efficiency.  Although we have no plans to incorporate a Zynq into our products, the very low latency of the AXI bus sounded like it could change this behaviour significantly.  If we could lower this DMA overhead of 6us (equivalent to sending 100x U8) to, say 2us (25 x U8) then our RT loop would actually be able to run faster (We are currently reaching 20kHz without problems).  If the overhead dropped to 0.4 us (5 U8) then we could actually consider operating a pipelined DMA transfer within our RT loop with data being transferred in several sequential packets instead of one "large" monolithic packet.  Between DMA calls we could then execute parts of our RT control loop and thus increase overall responsiveness (i.e. latency) of our loop.
Other considerations would be using two DMAs in parallel to achieve faster data transfer.  The lower the overhead, the more scenarios would benefit from this.
My considerations are mainly theoretical at the moment but it might come iin handy for future developments.
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant