How to set input delay and output delay when source Synchronous

Question

ClkIN is the board clock which is connected to the FPGA. Clkif is the generated clock from ClkIN. The Device's clk come from Clkif. So, how to set input delay and output delay in this scene(within my understand, this is Source Synchronous)?
The example in many document, the input delay and output delay setting all refer to board clock(within my understand, this is System Synchronous). In that scene, the input delay max = TDelay_max + Tco_max; input delay min = Tdelay_min + Tco_min; the output delay max = Tdelay_max + Tsu; output delay min = Tdelay_min - Th.
So, I want to know how to set input/output delay in the Source Synchronous.
In system synchronous, I set input/output delay such as:
create_clock -period 20.000 -name ClkIN -waveform {0.000 10.000} [get_ports ClkIN]
create_generated_clock -name Clkif -source [get_pins cfg_if/clk_tmp_reg/C] -divide_by 2 [get_pins cfg_if/clk_tmp_reg/Q]
create_clock -period 40.000 -name VIRTUAL_clkif //make virtual clock
set_input_delay -clock [get_clocks VIRTUAL_clkif] -min 0.530 [get_ports DIN]
set_input_delay -clock [get_clocks VIRTUAL_clkif] -max 7.700 [get_ports DIN]
set_output_delay -clock [get_clocks VIRTUAL_clkif] -min -0.030 [get_ports DOUT]
set_output_delay -clock [get_clocks VIRTUAL_clkif] -max 1.800 [get_ports DOUT]
*******************************************************************************************

Answer 1

So, first. Architecturally, the clock that you forward to your external device should not come directly from the clock tree, but should be output via an ODDR with its D1 input tied to logic 1 and the D2 tied to logic 0. This guarantees minimal skew between the output data and the forwarded clock.
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst (
.Q (Clkif_ff), // 1-bit DDR output
.C (ClkIN_BUFG), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable input
.D1 (1'b1), // 1-bit data input (positive edge)
.D2 (1'b0), // 1-bit data input (negative edge)
.R (rst), // 1-bit reset
.S (1'b0) // 1-bit set
OBUF OBUF_inst (.I (Clkif_ff), .O (Clkif_out));
This generates an output clock that is the same frequency as your input clock. This is consistent with your drawing, but inconsistent with your constraints - is the forwarded clock a 50MHz clock or a 25MHz clock?
I will assume your ClkIN goes to a BUFG and generates ClkIN_BUFG.  Your first constraint generates a 50MHz clock on the ClkIN port which will propagate through the BUFG to (among other places) this ODDR.
create_clock -period 20.000 -name ClkIN -waveform {0.000 10.000} [get_ports ClkIN]
Assuming your forwarded clock is supposed to be 50MHz, then your 2nd command is close to correct
create_generated_clock -name Clkif -source [get_pins cfg_if/ODDR_inst/C] -combinational  [get_pins cfg_if/ODDR_inst/Q]
With this done, you have successfully described the forwarded clock from your design. This is the clock that goes to your device, and hence should be the clock which is used to specify your input and output constraints.
set_input_delay -clock [get_clocks Clkif] -min 0.530 [get_ports DIN]
set_input_delay -clock [get_clocks Clkif] -max 7.700 [get_ports DIN]
set_output_delay -clock [get_clocks Clkif] -min -0.030 [get_ports DOUT]
set_output_delay -clock [get_clocks Clkif] -max 1.800 [get_ports DOUT]
If you want to get fancier, you could try adding a set_clock_latency to the forwarded clock to account for the board propagation of the clock
set_clock_latency -source TDtrace2 [get_clocks Clkif]
(But I haven't experimented with clock latency on a generated clock and I don't know for a fact that it works).
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