How to set input "Description" to mandatory?

Hi all,
How to set input "description", from infrastructure blueprint request form, to mandatory?
Thanks in advance.

Hi all,
How to set input "description", from infrastructure blueprint request form, to mandatory?
Thanks in advance.

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    ClkIN is the board clock which is connected to the FPGA. Clkif is the generated clock from ClkIN. The Device's clk come from Clkif. So, how to set input delay and output delay in this scene(within my understand, this is Source Synchronous)?
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    *******************************************************************************************

    So, first. Architecturally, the clock that you forward to your external device should not come directly from the clock tree, but should be output via an ODDR with its D1 input tied to logic 1 and the D2 tied to logic 0. This guarantees minimal skew between the output data and the forwarded clock.
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    .D2 (1'b0), // 1-bit data input (negative edge)
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    regard  by
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    Hi,
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    Regards,
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