Acquiring data in LabVIEW FPGA

Hello,
I am working on LabVIEW FPGA where I have to acquire data from a source and take its average. One way to do that is to keep adding every new signal to the sum f the older ones and then average.
However, I wish to store all the incoming values into a file and save it. But when I tried doing so, it gives an error saying "array size cannot be changed". With this constraint, I am unable to write the data into an array.
Please suggest.
Thank you.
Dheeraj Bharadwaj
IIT-Madras
Solved!
Go to Solution.

You need to acquire data, pass it to the RT, then log there. You cannot use build array on the FPGA because FPGA will not allow for dynamically allocating memory like this. You must preallocate the array then use replace array subset. A better way is to use DMA FIFOs. Have a look at the FPGA examples in LabVIEW for streaming data. Then, on the RT, you can just add in your file logging functions.
CLA, LabVIEW Versions 2010-2013

Similar Messages

I need drivers for Polytech Vibrometer OFV-5000 to acquire data using LabVIEW 10

I am using LabVIEW version 10.0f2, but I said ver 8.6.1 since mine wasn't there in the dropdown. I am new to Labview, but am trying to catch up fast since I think it is an absolutely amazing software. I use a Polytech Vibrometer OFV-5000 to measure displacements and velocities in the micro/nano lab, and wanted to acquire data on the PC via a RS232 cable. I needed my device drivers for the same. LabVIEW has drivers for Polytech Vibrometer OFV-3001, but they won't work for my model. Can anyone help me?

Well, as far as I know the Polytec-Controller, you can control the unit, set and read the setup (filter, ranges, laser on/off etc) values and the command set is in the manual.
Reading the velocity/displacement values seems not to be possible via RS232, only with S/P-DIFF Digital out. (The RS232 is slow and async , doen't make much sense unless you have a lot of memory in the controller ) usually you use the analog output and do the trigger/sync with your DAQ hardware
Have you asked polytec for a driver? I know they work a lot wiht NI hardware ...
We have a bunch of vibrometers, however since we (need to) use it as a primary standard, we do the decoding of the heterodyne signal by our own ...
Greetings from Germany
Henrik
LV since v3.1
“ground” is a convenient fantasy
'˙˙˙˙uıɐƃɐ lɐıp puɐ °06 ǝuoɥd ɹnoʎ uɹnʇ ǝsɐǝld 'ʎɹɐuıƃɐɯı sı pǝlɐıp ǝʌɐɥ noʎ ɹǝqɯnu ǝɥʇ'

Acquire data using Labview VI and process in matlab.

hello,
I wish to read data for two analog inputs using a NI DAQ USB 6356 and process it in matlab. I do not have matlab data acquisition toolbox. My Matlab code includes a mex file. I am planning to start with an example vi for data acquisition and put into it a matlab script node which would have my matlab code and will also call the mex file. I just want to know if this method is at all possible or if there is a better way to do it. At this time it would be sufficient if I just get a fixed number of samples and send it to Matlab, i.e I do not need any real time processing.
Umar.

Hi Umar,
Unfortunately we do not have Matlab within the office here so I'm unable to replicate your issue. On searching the details of the error you're experiencing on the MathWorks(R) website the explaination behind the error is:
Explanation:The number of left parenthesis is not equal to the number of right parenthesis in your expression.
Common causes:You added a left parenthesis or removed a right parenthesis from the line of code.
Solution: Count the number of left parentheses and right parentheses on the line of code. Verify that the quantity of the two types of parentheses are equal. Add in an appropriate number of right parentheses or remove extraneous left parentheses.
This suggests that the number of opening brackets does not equal the number of closing brackets, however on reviewing your code it seems that this is not the case. Would it be possible to run the Matlab Toolbox code on an older version of Matlab? It may also be worth reducing the "Samples_per_Channel" and "Sample_Rate" to much lower levels to see if the code executes.
Another solution might involve sampling the data within LabVIEW and then exporting the data to a *.csv data file which can then be easily imported for analysis within Matlab 2011. In this case invoking Matlab following data acquisition using a "Matlab Script Node" would be the best option.
Kind Regards
Jamie S.
Applications Engineer
National Instruments

FFT on LabVIEW FPGA

Hello Everyone,
I am doing a project in which i have to done FFT on data on LabVIEW FPGA. The data is actually a pixel value of an image which are first converted to imaginary parts and then their exponential is to computed, after taking exponential their FFT is to perform. I am new to Labview FPGA but know something about LabVIEW. If any one can guide me from where to start and how to do this, it will be of great help to me. I studied a tutorial on NI website but didn't get much out of it. I have NI cRIO-9024 LabVIEW FPGA. Any help will be appreciated.
Thanks
Regards

Hello!
We don’t have any finished VI’s shipping with the LabVIEW FPGA Module that does FFT. However if you can VHDL or have access to HDL IP Cores you are able to make use of the HDL node and implement it yourself. Then tests needs be to done in order to find if the VI can execute fast enough. If you search on HDL node on our website you will find more information about how to implement code using that function. You can also provide information to our R&D that you would like to see this feature in the future here:
http://digital.ni.com/applications/psc.nsf/default?OpenForm&temp1=&node=
Regards,
Jimmie Adolph
Systems Engineer Manager, National Instruments Northern Region
Bring Me The Horizon - Sempiternal

How to acquire data through multiple channels in parallel using PXI 6070 E, PXI 4071 and LabVIEW?

Hi,
I am using NI LabVIEW, NI PXI 4071, and NI PXI 6070E to measure current through a variable resistance. Now, I am using one channel from SCB-68, but I want to add another channel in parallel so that I can have two resistors instead of one that I cam measure current through them.
I have attached a Pdf file showing the setup for hardware in use and LabVIEW code also.
Can anyone look at these files and give me guide lines or ideas that can help me resolving this issue, please.
Thanks in advance.
Best Regards,
Shaheen.
Solved!
Go to Solution.
Attachments:
IV copy for HS.vi ‏55 KB
Layout of NI Cards.pdf ‏248 KB

Your 4071 can only do one measurement at a time. Your DAQ cannot measure resistance either nor has it got any analogue inputs.
However, you could use a multiplexer and multiplex your 4071 DMM. This wont give you simultaneous measurements but can acquire data one after the other, the speed is obviously dependent on the multiplexer you choose!
Hope this helps.
Beginner? Try LabVIEW Basics
Sharing bits of code? Try Snippets or LAVA Code Capture Tool
Have you tried Quick Drop?, Visit QD Community.

Creating multiple tasks in labview fpga

Hi,
I need to create multiple tasks in labview fpga....I need to set one update period in each task so that i can make my while loop run at this rate everytime my input frequency changes....How do i do this?

Hi,
just to be sure: You are talking about multiple tasks on the FPGA to acquire data? Or do you want to have multiple tasks on the host to display the data?

LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)

Hello NI forums,
Question:
See the attached picture from a modified version of the LabVIEW DRAM FIFO example. It probably explains my question more effectively than the paragraphs below.
What is the difference to the LabVIEW / Xilinx compiliers, if any, between placing two independent branches of code in the same SCTL, versus placing them in individual SCTLs (in the same clock domain)?
Misc. comments:
I have briefly experimented with this concept using the included LabVIEW DRAM FIFO example (example finder >> Hardware Input and Output >> FlexRIO >> External Memory >> Simple External Memory FIFO.lvproj).
I compiled the default example (the read and write interfaces are in separate 40MHz SCTLs) five separate times. Then I put the read and write interfaces in the same 40MHz SCTL and compiled another five times. The result (when both read and write interfaces were in the same SCTL) was a reduction in resource usage (according to the compilation summary).
However, due to my lack of knowledge I'm hesitant to conclude that placing everything in one SCTL is always the best option. For example, I do not know what is created 'behind the scenes' with each SCTL. Perhaps putting independent branches of code in separate SCTLs makes it possible to route clock, reset, implicit enable, etc. signals more effectively.
Background information:
My task involves acquiring 2 channels of analog data using the NI 5772 and PXIe-7966. Data acquisition takes place in a 200MHz SCTL, and downstream processing is performed in a 100MHz SCTL.
During a vast majority of the 100MHz SCTL processing stages of the FPGA VI, the 2 channels of data do not interact with eachother. So it would be easy for me to place them in separate 100MHz loops if doing so would somehow help the design (timing, resource usage, etc.).
Thanks!
Attachments:
question.png ‏76 KB

Intaris
Trusted Enthusiast
Posts: 3,264
Re: LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
‎10-28-2014 12:11 PM
Just out of interest, what is the resource usage differential between the two versions?
In response to the above comment,
This is a little embarrassing, but it seems like the resource usage is similar than I initially thought for this particular example. I think the previous compilations that I based my assumption on coincidentally used more resources in the 2-SCTL loop case. I just compiled each version two additional times (see below).
Here's the version with everything in one loop:
Device Utilization
Total Slices: 17.6% (2587 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4855 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 16.9% (2493 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4858 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Here's the version with the read and write in separate loops:
Device Utilization
Total Slices: 16.4% (2407 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4852 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 19.4% (2859 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4859 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)

Use LabVIEW FPGA as a DAQ and detect peak

Hi everyone, need your help now.
I want to use Labview to encode a FPGA to achieve following function：
1.Acquire data as a DAQ from a Photodetector
2.then use peak detect VI to measure the peak information
3. some simple mathematical operations
is it possible for me to achive all these only using one FPGA? and is it OK to connect DAQ's output and the input of the peak detect VI?
thanks a lot. I am a beginner, so it confused me a lot.

Hi
What is you hardware? cRIO? FlexRIO? And what your signal type? Anolog or digital?
You can refer to the help of Peak detect.vi to comfirm if the data (sigle point integer or integer array ) can be wired directly. I am afraid you can not wire the FPGA IO OUT directly to the Peak detect.vi, but you can create a array for the data and then use the peak detect.vi

How to acquire data from multiple dataports at the same time

Hi,
I studied the multithreading section of Labview, but still have no idea
how to make it work. Let me briefly explain my situation. I need to
develop a program that can control and acquire data from 4 serial
ports. I have 4 buttons to control starting or stopping acquisation
from the corresponding port. Every acquisation process is a while loop.
How can I start a new acquisation loop (eg. from COM2) while the loop
for COM1 is still running? In other words, I wish the 4 loops running
independently, and are controlled by their corresponding buttons only.
Thanks for any suggestion.
Jin

Hi Anonymous,
If I were you, I'd create one VI (call it Port.vi) to listen to one port - then make it reentrant. Drop 4 copies of Port.vi on your Main diagram. Port.vi inputs could include a VISA reference, a "Start/Stop" notifier and maybe a "Quit" occurance. Wire to each copy of Port.vi a unique VISA reference and a unique "Start/Stop" [boolean] notifier - let all the copies share the same Quit Occurance.
In Main, have one event case for each of your stop buttons. When a button is pressed, send the appropriate Start/Stop notifier!
... of course you could accomplish the same thing with four identical loops right in your main diagram, but the more complex the port-handling gets, the easier it will be to manage in one place instead of four.
Cheers!
When they give imbeciles handicap-parking, I won't have so far to walk!

How to acquire data from 2 chs of the same DAQ card at different sampling rate

I am using single DAQ card (either 6013 or 6014) in my system i want to acquire data from 2 (or more) channels with following requirements
1. sampling rate of each channel should be independant of each other (say one is 20 Hz and other is 15 kHz)
2. data from all the channels should be acquired simultaneously.
3. coding must be done using DAQmx VIs
I have tried out following things
1. I created separate task for each channel: i found out that two tasks can not run simultaneously even though the channels are different
2. I tried out single task with two channels included in it. and i used 'channels to Read' property to determine from which ch. i want to acquire data: this method works fine if the sampling rates are same. but if i change the sampling rate of one channel it gets reflected in other channels as well.
can somebody help me out to solve this problem.
i will appreciate if somebody can post the sample code as my deadline is approaching
Tushar Jambhekar
[email protected]
Jambhekar Automation Solutions
LabVIEW Consultancy, LabVIEW Training
Rent a LabVIEW Developer, My Blog

Hi Dennis Knutson
Thanks for your suggestion.
Tushar Jambhekar
[email protected]
Jambhekar Automation Solutions
LabVIEW Consultancy, LabVIEW Training
Rent a LabVIEW Developer, My Blog

Acquiring data continuously with a start and stop trigger

I am currently acquiring data continuously (1000 samples at 5k/s) using a start trigger to start the acquisition and stopping the acquisition with a digital line. The problem with this is that I want the acquisition to stop immediately on a trigger, in otherwords I don't want it to finish with 500 or 200 samples of useless data. I am using a PCI 6024 E. Any suggestions would be appreciated.

The trick will be to minimize the number of post-trigger scans that will occur after your stop trigger. The stop (reference) trigger requires a minimum of 2 post-triggered scans. Therefore, the way to stop your acquisition as soon as possible is to configure your stop trigger to have only 2 post-triggered scans.
I've included a little bit of code to illustrate this in LabVIEW 7.0. The number of post-trigger scans will equal the buffer size less the number of pre-trigger scans. Since the minimum number of post-triggered scans is 2, we'd have to set the number of pre-trigger scans to the buffer size less 2. This is wired as the minimum number of pre-trigger scans acquired input to the AI Control.vi in the example.
This should do what you're
after. Best of luck to you as you get this all put together.
Jim Laudie
Applications Engineer, National Instruments
Attachments:
example.vi ‏85 KB

How to download a table of data to the FPGA

I m using an PCI7813R FPGA board and I'm trying to download a table of data into the FPGA. How can I do this as fast as possible and so I can easily index each data row in the fpga. The length of the table can be variable from run to run. A block of memory where in I could write from the host would be the best solution I think, but I don't think this is possible.
Does anyone have some ideas about doing this?

Hi esrgb,
As you probably noticed, it's not possible to use a table in LabVIEW FPGA. Therefore you will have to go through an array. Keep the following in mind however when using an array:
http://digital.ni.com/public.nsf/websearch/80C9808E454DCBC286257093005B9EB6?OpenDocument
Now unlike you think, there is a block of memory available on the FPGA itself which you can address straight from your FPGA code, for examples see:
http://sine.ni.com/apps/we/niepd_web_display.display_epd4?p_guid=BE211EB859136066E034080020E74861&p_node=201268&p_source=External
There is also a tutorial available which discusses the use of clusters and array in general in LV FPGA.
http://zone.ni.com/devzone/conceptd.nsf/webmain/2bf2813a4beb80c38625700b007da74a
Kind Regards,
Wouter Van Hoof
National Instruments

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Labview FPGA encoder reading

hello,
I an new in LabVIEW FPGA programing so I would appreciate any help. I am using sb-rio 9636 card and optocoupler for speed messaurment of DC motor. I have conected everyting right and the sensor is giving me date. But messauring the speed the oscilations of sensor data are huge. I am not changing the speed and motor continiousliy is rotating in the same speed but data are not the same. For example im 12 V that is the max speed motor schould rotate in 6500 rpm/min but in one second it is showing 6500 and in the other 5500 rpm/min. think that there is not problem in the code but that the messaurment are not reliable. I will put my code. I need to know is there anz other way to do encoder readings.
Thank you

I don't see anything in your loop that guarantees the timing of your sampling of the digital encoder pulses. It appears you expect that loop to run at 1MHz based on the uS unit label on your time of flight indicator.
Because you are using front panel indicators for some of your calculation variables, I can't see all the numbers going into your calculations.
How much variance do you see in the time of flight measurement on your front panel? You must remember that you are making measurements in whole integers of uS. How much change in the RPM calculation do you see if the uS measurement drifts by 1 uS?
If the impact of 1uS change in pulse to pulse measurement has a big impact on your calculation, then you will need to adjust your algorithm to get a more precise measure of the time of flight.
Some ideas:
The faster your sampling loop runs, the more likely you will sample the signal right after the pulse transistion. Consider using a Single-Cycle Timed Loop to sample at speeds in the 40MHz (25ns period) range. This will give you more precision. One risk I can't rule out in your existing code is that you may be sampling slow enough that in some cases you miss a pulse completely. If you want to ensure that you do not miss any pulse edged, then you must ensure that the loop is sampling at least 2x the frequency of your pulse train, assuming the pulses have a clean 50% duty cycle. If that duty cycle is not 50%, then the maximum sampling period must be shorter than the shortest pulse you expect.
Rather than measuring the time difference from pulse to pulse, measure the time of 10 pulses, or 1000 pulses, or some other larger number. This averages a larger number of pulses so that the difference of 1us resolution has less impact on the calculated measurement.

Labview FPGA: Why not have local variable without indicator?

In Labview FPGA, to transfer data among parallel loops, there are three ways or maybe more, local variable, global variable and block memory. The problem with local variable is that it needs an indicator along with, not like global variable. I was thinking why Labview doesn't make a kind of local variable not need indicator? I guess local variable itself doesn't cost resource much compared to global variable, however when it comes into indicator, it will cost more. Just an idea, though. I guess there is a reason NI doesn't do that.

As in Labview document, global variable can be used for transfer data among VIs, which local variable isn't capable of.
Global variable is not always a better solution. From my experience, it is still unclear among different compilations using local vs global in terms of resources. A thread here http://forums.ni.com/t5/LabVIEW/FPGA-global-variables-vs-front-panel-items/td-p/1407282 talks about that too.
Stephen, is there any documents say that global makes timing worse? I didn't see this noticeable.

Acquiring data in LabVIEW FPGA

Similar Messages

Maybe you are looking for