Labview FPGA encoder reading

hello,
I an new in LabVIEW FPGA programing so I would appreciate any help. I am using sb-rio 9636 card and optocoupler for speed messaurment of DC motor. I have conected everyting right and the sensor is giving me date. But messauring the speed the oscilations of sensor data are huge. I am not changing the speed and motor continiousliy is rotating in the same speed but data are not the same. For example im 12 V that is the max speed motor schould rotate in 6500 rpm/min but in one second it is showing 6500 and in the other 5500 rpm/min. think that there is not problem in the code but that the messaurment are not reliable. I will put my code. I need to know is there anz other way to do encoder readings.
Thank you

I don't see anything in your loop that guarantees the timing of your sampling of the digital encoder pulses. It appears you expect that loop to run at 1MHz based on the uS unit label on your time of flight indicator.
Because you are using front panel indicators for some of your calculation variables, I can't see all the numbers going into your calculations.
How much variance do you see in the time of flight measurement on your front panel? You must remember that you are making measurements in whole integers of uS. How much change in the RPM calculation do you see if the uS measurement drifts by 1 uS?
If the impact of 1uS change in pulse to pulse measurement has a big impact on your calculation, then you will need to adjust your algorithm to get a more precise measure of the time of flight.
Some ideas:
The faster your sampling loop runs, the more likely you will sample the signal right after the pulse transistion. Consider using a Single-Cycle Timed Loop to sample at speeds in the 40MHz (25ns period) range. This will give you more precision. One risk I can't rule out in your existing code is that you may be sampling slow enough that in some cases you miss a pulse completely. If you want to ensure that you do not miss any pulse edged, then you must ensure that the loop is sampling at least 2x the frequency of your pulse train, assuming the pulses have a clean 50% duty cycle. If that duty cycle is not 50%, then the maximum sampling period must be shorter than the shortest pulse you expect.
Rather than measuring the time difference from pulse to pulse, measure the time of 10 pulses, or 1000 pulses, or some other larger number. This averages a larger number of pulses so that the difference of 1us resolution has less impact on the calculated measurement.

Similar Messages

Can i use Handle C with the LABVIEW FPGA module?

Hi,
Can i use Handle C with the LABVIEW FPGA module? I am working with CompactRIO right now so, i want to know weather i can use Handle C with CompactRIO.Can i access FPGA in compactRIO independant of LABVIEW means can i program it without using LABVIEW?
regards,
Vishnu.

Hi Vishnu,
Although we don't support Handel-C directly, it is possible to design your algorithms using 3rd party tools or system integrators and consume them from a top-level LabVIEW VI. The webcast at http://zone.ni.com/wv/app/doc/p/id/wv-268 shows an example of how you can use IP from C-based tools provided by Celoxica in the LabVIEW FPGA environment.

Use LabVIEW FPGA as a DAQ and detect peak

Hi everyone, need your help now.
I want to use Labview to encode a FPGA to achieve following function：
1.Acquire data as a DAQ from a Photodetector
2.then use peak detect VI to measure the peak information
3. some simple mathematical operations
is it possible for me to achive all these only using one FPGA? and is it OK to connect DAQ's output and the input of the peak detect VI?
thanks a lot. I am a beginner, so it confused me a lot.

Hi
What is you hardware? cRIO? FlexRIO? And what your signal type? Anolog or digital?
You can refer to the help of Peak detect.vi to comfirm if the data (sigle point integer or integer array ) can be wired directly. I am afraid you can not wire the FPGA IO OUT directly to the Peak detect.vi, but you can create a array for the data and then use the peak detect.vi

How can I install (download) a Labview FPGA code onto Altera FPGA chip using Labview FPGA module?

Hi there
Guys i'm a very new labview user (PhD student), my project is about ( design and implementation of a high speed-yet sophisticated system using Labview environment then install this project's code (using Labview FPGA module) onto Altera-made FPGA chip).
so kindly, can any body help me in this?...is there any way to connect labview with Altera FPGA?...please anything would be said 'd be of great benifits
thanks a lot in advance.

as previously mentioned, labview fpga only supports national instruments targets utilizing xilinx fpgas. the hdl generated by labview fpga is encrypted and cannot be used to synthesize a design outside the labview fpga design flow.
however, if you must use labview for your project, it might be possible for you to design the system in labview and use one of the labview embedded modules ( http://www.ni.com/embedded )to generate c code which you can then port to systemc and compile for the altera fpga. i'm not saying it will be easy, but it should be possible.

Creating multiple tasks in labview fpga

Hi,
I need to create multiple tasks in labview fpga....I need to set one update period in each task so that i can make my while loop run at this rate everytime my input frequency changes....How do i do this?

Hi,
just to be sure: You are talking about multiple tasks on the FPGA to acquire data? Or do you want to have multiple tasks on the host to display the data?

LabVIEW FPGA driver for Xilinx SPARTAN 3E Starter Board

i need drivers for spartan 3E .

If you are at a university that has a site license for the FPGA module, the following might be of interest to you:
Using LabVIEW FPGA with the Xilinx SPARTAN-3E XUP Starter Kit
See also this discussion.
Quote from the license agreement:
...INSTALLATION AND USE OF THE LABVIEW FPGA TARGET MODULE FOR THE XILINX SPARTAN-3E STARTER BOARD (THE “TARGET MODULE”) IS LIMITED TO ACADEMIC INSTITUTIONS THAT HAVE A VALID, CURRENT “ACADEMIC TEACHING LICENSE” FROM NATIONAL INSTRUMENTS FOR THE LABVIEW FPGA MODULE. THIS TARGET MODULE MAY ONLY BE USED FOR INSTRUCTIONAL PURPOSES, SUBJECT TO THE TERMS AND CONDITIONS OF THE NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT THAT ACCOMPANIES THE SOFTWARE...
LabVIEW Champion . Do more with less code and in less time .

Labview FPGA for beginners.

Hello.
I have no idea what labview is and how to work with this. I have had some experience with Xilinx 12.1 EDK (microblaze and VHDL).
I tried to install labview and labview fpga module. It asked for some drivers and I continued, the program said that it will ask for the drivers later.
But, beside that, do you have any training flow to suggest? Should I start with labview or is it not necessary? After that, should I start with CVI or FPGA? I am confused. Any help is welcomed!
Thanks,
Bill.

See this video's to get start with labVIEW and more video's you can find in youtube. Also, get in touch with forum especially about FPGA questions or read the history question targeting to your design area.
http://zone.ni.com/devzone/cda/tut/p/id/7466
I never use FPGA codes or concepts in labVIEW but I am looking to learn now.

Labview fpga with nexys 2

hi my friends I want to know I can use labview FPGA with nexys 2 and there are some device about this FPGA (nexys 2) because we have this circuit board and we want to do the project with labview you can found some information about nexys 2 in this file and thank you for your help
Attachments:
Nexys2_rm.pdf ‏986 KB

Hello,
As this forum thread states, LabVIEW FPGA is only for the SPARTAN-3E XUP Starter Board and NI Reconfigurable I/O devices. Even though the nexys 2 is based from the Spartan 3E, we can’t be sure that the driver that we release for the Spartan 3E starter board works for the nexys 2.
Regards,
Daniel REDS
RF Systems Engineer
Help us grow.
If a post solves your question, mark it as The Solution.
If a post helps, give Kudos to it.

LabVIEW FPGA PMW modulation for L298n H-bridge

Hello to everyone,
I am new in LabVIEW FPGA programing and I have a couple questions, so I would be grateful if you could answer me. For my final work I have to control the speed and direction of DC motor using sb-RIO 9636 and H-bridge L298n. In attachments you can find scheme of the H- bridge and my program. I have conected In1(pin 5 of L298n) to digital pin 1 of the card, In2(pin 7 of L298n) to digital pin 2 of the card and changing the state of the pin I change the direction of the motor(I know that the one In should be Low and the other High so the motor can rotate in one or the other direction). PWM(Enable pin of the L298n pin 6) I have conected to DIO3.
PWM signal I cretaed is shown in picture.
My questions are:
1.Will loop timer I used, provide that period of signal is lenght I specify in the control(for example if I put 20 000 will the period be 20000 s)?
2. Can I vary the duty cycle changing the control Waiting (DIO3 is HIGH for a couple of us, then it sets LOW, and then all that repeats )?
3. Earlier I thaugt that PWM signal I should send in both IN1 and IN2, and that the Enable pin is used to stop or start the motor. I tried that and the motor was rotating different speed, and I could stop or star the motor with enable pin, sending it HIGH OR LOW, but I could not change the direction of the motor. So my other option was to conect the pins as I explained at the begining. My question is: Should I PWM conect to the enable pin, and will thah work?
Thank you

I found a couple of resources that deal with PWM on the FPGA and motor control - they might be helpful to reference as you look for answers to your questions.
Developing a PWM Interface using LabVIEW FPGA
http://www.ni.com/white-paper/3254/en/
CompactRIO Motor Control Basics Tutorial
http://www.ni.com/pdf/labview/us/compactrio_motor_control_basics.pdf
PWM Output With LabVIEW FPGA
http://www.ni.com/example/26499/en/

LabVIEW FPGA support

Respected Sir,
Is LabVIEW FPGA support for kit numbered ML-505 ( FPGA Type : Virtex 5 LX110T ) available or not ? If yes, where it is?
Solved!
Go to Solution.

The only FPGAs that are supported by LabVIEW FPGA are the ones included in National Instruments hardware. You cannot target other FPGA kits using LabVIEW.

Labview FPGA: Why not have local variable without indicator?

In Labview FPGA, to transfer data among parallel loops, there are three ways or maybe more, local variable, global variable and block memory. The problem with local variable is that it needs an indicator along with, not like global variable. I was thinking why Labview doesn't make a kind of local variable not need indicator? I guess local variable itself doesn't cost resource much compared to global variable, however when it comes into indicator, it will cost more. Just an idea, though. I guess there is a reason NI doesn't do that.

As in Labview document, global variable can be used for transfer data among VIs, which local variable isn't capable of.
Global variable is not always a better solution. From my experience, it is still unclear among different compilations using local vs global in terms of resources. A thread here http://forums.ni.com/t5/LabVIEW/FPGA-global-variables-vs-front-panel-items/td-p/1407282 talks about that too.
Stephen, is there any documents say that global makes timing worse? I didn't see this noticeable.

LabVIEW FPGA Sine Wave Generator Reset Input Behavior

I would like to know what the output from the Sine Wave Generator express VI is while the reset input is true, and what happens to the output immediately after the reset input is set false.
I need to generate a regular sequence of positive half-cycles of a sine wave, with an arbitrary delay between them that is not related to the actual frequency of the sine wave. So my plan is basically to periodically fire a trigger in the fpga software that resets a sine wave generator and directs its output to an analog output until the sine wave goes negative, at which point the analog output is set to 0 until the next trigger.
Thanks

Muchas gracias por responder steve.bm
El problema que tengo es el siguiente, estoy desarrollando un proyecto en el cual uso los conversores DAC y ADC de la tarjeta FPGA Spartan 3E para lo cual use como base el proyecto que esta subido por la NI que se encuentra en uno de los enlaces que me dejaste,( Lesson 8 - Linking Existing VHDL Code from WebPACK into LabVIEW FPGA) del mismo solo modifique para usar el ADC y el DAC mediante el cual adquiero una señal senosoidal y la tengo que reconstruir, el problema es que como uso un generador de señal de laboratorio al ingresar la frecuencia de muestreo para obtener una buena reconstruccion, la frecuencia se baja lo cual en el proyecto real no podra pasar ya que la frecuencia ya en proyecto final la adquiero de la red electrica publica pero ahora para pruebas estoy con un generador, la verdad no se que pasa porque tiene un retrazo la señal.....
Te parece si te puedo dejar mi proyecto subido en enlace para que lo revices ??

How to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.

how to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.
attachment:a sine signal using dds theory. Hope to get some help. Thanks!
Attachments:
FPGA DDS SineGen IP.vi ‏42 KB

you need to increment the "accumulator increment" during the duration of the chirp. the "accumulator increment" controls the frequency of the DDS cycle. by increasing it's value, you are increasing the frequency. the math for increment values follows the same math as determining the frequency to increment value.
Stu McFarlane
Viewpoint Systems, Inc.

Problems getting started with LabVIEW FPGA

Two (probably) related questions:
1. I am trying to get started with LabVIEW FPGA, and I am having trouble using a host VI to test my FPGA VI. I started with a basic QAM modulator VI, to be run on the FPGA, and I have reached the point where I need to verify the logic and timing with this VI running on the development computer with simulated IO. I have tried various combinations of putting the code inside single-cycle timed loops vs not; putting the modulator block directly into the host VI, and using the "FPGA reference" block. When neither the host VI nor the modulator VI use a single-cycle timed loop, I see correct behavior. In every other case, the output of the VI is either absent or incorrect. I need to use a single-cycle timed loop in the FPGA VI to properly verify timing behavior (as far as I know), so the one functioning case is not enough for me.
I'm sure there is a key step I'm missing or misunderstanding, but I have not been able to figure it out myself yet. I've attached my modulator diagram as well as two different attempts at host VIs. I can share other information, but I'm not sure what is most relevant.
2. I am also trying to test a simple wrapper VI for the Xilinx FFT block, and I am having trouble accessing FIFOs inside the host VI. I thought this would be relatively straightforward, but when I tried to change the "method" on an "invoke method" block, there were no options for accessing FIFOs, as I understood there should be. This is a total roadblock for me. These two diagrams are also attached, the test diagram shows the options available to me for the "invoke method" block.
Labview 2013, PXIe-7965R, PXIe-8133 controller.
I had to combine the diagram images; in case they are hard to follow this way, see the individual images here: http://imgur.com/a/oB6OD .
Thanks in advance for any suggestions.
Attachments:
mod_all.png ‏68 KB
fft_all.png ‏52 KB

Hello Monguin61
If you are having problems reading from DMA FIFO's you should test them using a very simple code to understand their behavior. First, you could start taking a look to the linked documents:
Reading DMA FIFOs from Host VIs (FPGA Interface)
Using DMA FIFO to Develop High-Speed Data Acquisition Applications for Reconfigurable I/O Devices
FIFO.Read (Invoke Method)
Then you could test and analyze a simple example to understand how it works, for example this one: Simple DMA FIFO Example for FPGA.
Check the references when you are using DMA FIFO's, I noticed you did not connect them in the second picture attached.
Regards
Frank R.

LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)

Hello NI forums,
Question:
See the attached picture from a modified version of the LabVIEW DRAM FIFO example. It probably explains my question more effectively than the paragraphs below.
What is the difference to the LabVIEW / Xilinx compiliers, if any, between placing two independent branches of code in the same SCTL, versus placing them in individual SCTLs (in the same clock domain)?
Misc. comments:
I have briefly experimented with this concept using the included LabVIEW DRAM FIFO example (example finder >> Hardware Input and Output >> FlexRIO >> External Memory >> Simple External Memory FIFO.lvproj).
I compiled the default example (the read and write interfaces are in separate 40MHz SCTLs) five separate times. Then I put the read and write interfaces in the same 40MHz SCTL and compiled another five times. The result (when both read and write interfaces were in the same SCTL) was a reduction in resource usage (according to the compilation summary).
However, due to my lack of knowledge I'm hesitant to conclude that placing everything in one SCTL is always the best option. For example, I do not know what is created 'behind the scenes' with each SCTL. Perhaps putting independent branches of code in separate SCTLs makes it possible to route clock, reset, implicit enable, etc. signals more effectively.
Background information:
My task involves acquiring 2 channels of analog data using the NI 5772 and PXIe-7966. Data acquisition takes place in a 200MHz SCTL, and downstream processing is performed in a 100MHz SCTL.
During a vast majority of the 100MHz SCTL processing stages of the FPGA VI, the 2 channels of data do not interact with eachother. So it would be easy for me to place them in separate 100MHz loops if doing so would somehow help the design (timing, resource usage, etc.).
Thanks!
Attachments:
question.png ‏76 KB

Intaris
Trusted Enthusiast
Posts: 3,264
Re: LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
‎10-28-2014 12:11 PM
Just out of interest, what is the resource usage differential between the two versions?
In response to the above comment,
This is a little embarrassing, but it seems like the resource usage is similar than I initially thought for this particular example. I think the previous compilations that I based my assumption on coincidentally used more resources in the 2-SCTL loop case. I just compiled each version two additional times (see below).
Here's the version with everything in one loop:
Device Utilization
Total Slices: 17.6% (2587 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4855 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 16.9% (2493 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4858 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Here's the version with the read and write in separate loops:
Device Utilization
Total Slices: 16.4% (2407 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4852 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 19.4% (2859 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4859 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)

Labview FPGA encoder reading

Similar Messages

Maybe you are looking for