ADC/DAC 14Bit to 16Bit conversion

Question

Hi,
I am trying to understand how the signals are affected by the ADC and DAC, respectively, of the NI5641R. From the datasheets I know that both the ADC and the DAC support a 14Bit conversion. Now, from the ADC I receive 2 (I and Q) I16 values, so I guess the binary of these signals look something like 00xx'xxxx'xxxx'xxxx b.
For a first application I just want to have a NULL-Modem. Thus, those bits are directly sent to the DAC. But in some examples it is stated, that the I16 values need to be adapted to a 14Bit value by shifting the I16 by 2. If I do that with my value from the ADC my output signal would be something like 0000'xxxx'xxxx'xxxx b, which thus is NOT the same as my input singal. Or is there something wrong?
Another question which concerns the ADC and DAC is about their power levels: If I build a NULL-Modem and connect a signal with a power-level of -20dBm to the ADC, the signal on my FPGA has a level of -30dBm and after the DAC a level of -40dBm. Are the losses of 10dB in each stage normal?
Thanks for the help.
Kind regards
Roman Gassmann 

Answer 1

Hi Roman,
Sorry for the delay in this reply, but I have been looking
over your code and believe I know the cause of the issue I was seeing and in
turn have shed some light on what you have been experiencing. I did see a drop
of about 10dB but only at lower AI spans at higher spans I saw no drop and also
no spurs. You did not mention any spurs in your previous post but when I used a
sine tone to test your VI I saw  images
equal in power to the fundamental. After tracking the cause of this down I believe
I know what is causing your issues. When you move from the ADC clock to the
RTSI clock you are not gating your FIFOs off of a data valid signal(read
inversed timeout). This is causing your FIFO to fill with zeros intertwined
with your data on some clock cycles essentially bringing every other sample
back to zero and creating a aliasing effect. 
My suggestion is to use logic similar to the example below to ensure
that when you are crossing clock domains you are only writing valid data into a
FIFO, the false case only contains a false constant wired to the boolean output. I hope this clears things up let me know if you have any further
questions.
JaceD
Signal Sources Product Support Engineer
National Instruments