ADSP-21020 EZ-LAB Eval-board interface VI

Does
anyone have experience with developing a LabVIEW serial interface to the
ADSP-21020 EZ-Lab evaluation board? It is part of a legacy system that
currently requires us to upload files using the DOS prompt. I am unable
to find any good documentation for the original lab21k interface program
provided by Analog Devices and then no longer offer any support for this system. We would like to incorporate this into our LabVIEW
interface. Any ideas?

Bob,
Let me preface this reply by letting you know that I am not terribly familiar with the ADSP-21020.
From what I understand (based on a half hour of reading what I could find on the internet) it requires that you compile your C program using a particular compiler and then upload it to the board for execution.
Are you trying to use LabVIEW to automate the uploading of your already compiled application? If so you may be able to do so using serial communication if you know the required protocol. I was unable to find any documentation about how to interface with this board which makes it hard for me to suggest any possible ways to tackle this problem.
If anyone out there knows more about these particular devices and can help please do chime in.
Regards,
Simon H
Applications Engineer
National Instruments

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Looking forward for your guidance in resolving the same
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Chris McCrory wrote in message
news:8oitvr$9s4$[email protected]..
> Has anyone experienced problems when installing NI-DAQ 6.7 on Windows
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Hi,
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Hi GerdW,
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it works with your solution, but it create another problem with another vi (see picture).
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SASA
Attachments:
synamic-simple-Interface-problem.jpg ‏47 KB

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ISE 14.4
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The Xilinx_Answer_43879_debug.pdf guide
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ug473_7Series_Memory_Resources
ug586_7Series_MIS_v2_3
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http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/MIG-init-calib-compleate-takes-5-seconds-to-complete/m-p/571435#M7763
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http://forums.xilinx.com/t5/Simulation-and-Verification/MIG-7-series-simulation-init-calib-complete-issue/m-p/622235#M13053
http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/A-problem-about-init-calib-complete/m-p/534475#M6975
http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/Init-calib-complete-never-goes-high-using-VC707-Development/m-p/424356#M8802
http://www.xilinx.com/support/answers/63463.html
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Steffen

Any idea anyone?
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Otherwise it might be a good idea to include this issue in http://www.xilinx.com/support/answers/51899.html

ADSP-21020 EZ-LAB Eval-board interface VI

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