Apparent Bitfile corruption in VI

I was writing a small Host VI to test certain FPGA problems we've been having in the last time.
Test was working fine, and I was refining things step by step.  Then I started getting errors "If using external clocks blah blah blah" and was getting errors writing controls in the FPGA code but reading the indicators was working fine.  I tried restarting LV, restarting the hardware and nothing was able to remedy the problem.
I finally switched Bitfile (in my "Open FPGA Reference" node) and suddenly the problems went away.  I changed BACK again and things worked fine.
This is a very worrying behaviour.  I have both VI and Bitfile on a shared network path and the source for the host VI is NOT set to seperate compiled code.  During testing, every 8-12 times I re-run the VI after making trivial changes the Bitfile fails to work as expected.
Seeing how we're trying to nail down errors which are occurring approximately 1% of system restarts, this is a VERY worrying sign.  Anybody got any experience with this?  I'm using LV 2012 SP1 on WinXP running in a Virtualbox VM which in turn runs on a Win7 64-bit machine.  My XP machine has the 3GB switch with USERVA set to 2900.
Shane
Say hello to my little friend.
RFC 2323 FHE-Compliant

As soon as I see the problem again I'll send a copy of the corrupted VI so that it can be analysed to see what's wrong.  I'll also send a copy of a non.corrupted VI as comparison.  How about that?
It doesn't happen VERY often, but as soon as it happens again I'll make sure to post.
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant

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