Artix-7 user i/o pins damage

Question

I'm facing problems with Artix-7. Our design has an ADC with CMOS (LVCMOS25) outputs interfacing with Artix-7 XC7A200T (FFG1156) through CMOS buffers. Our ADC is 16 bits, 130 MSPs connected to User I/O pins of the same bank. By some reason some of the user I/O pins of the FPGA that interfaces with digitized data pins of the ADC are damaged. We have produced 6 FPGA boards and all of them presented problems on the same pins. I have identified that:
- The clamping diodes of the damaged user I/O pins are working well (I have measured it)
- The FPGA configuration is correctly set for LVCMOS25 and pull-up
- Even when setting the input voltage as logic level "0" on the damaged user i/o pins, I always read logic level 1
- The power-up/down sequence for VCCO and VCCaux is ok and the voltage levels are well beyond 2.625 Volts during TVCCO2VCCAUX
- All the input voltages of the user i/o pins are well within the limit of 0 Volts and 2.5 Volts. Even in the case of driving the inputs with high voltages, peak voltages driven by CMOS buffers cannot provide enough current to damage the input buffer due to the fact that the clamping diodes will protect the i/o (remember I said that the damaged pins have clamping diodes working well)
- I have already set the damaged user I/O pins as input, output, pull-up, pull-down, different voltage levels, but they are not working and are always set to logic level "1".
Questions:
- Do you have a suggestion on what can cause damage to the user i/o pins considering that I have 16 identical LVCMOS25 inputs and 2 of them are by some reason being damaged?
- Can I have access to the internal user i/o pin electrical scheme?
- Can grounding problems damage user io pins?
- Has anyone reported similar problems?
Regards
  Rafael Baron
 

Answer 1

r,
- Do you have a suggestion on what can cause damage to the user i/o pins considering that I have 16 identical LVCMOS25 inputs and 2 of them are by some reason being damaged?
My first guess is that it has been damaged by electrostatic discharge (ESD) events.
As you state, the diode is still there, and it would be unlikely to fail from ESD.  But the ESD would blow out the gate of the transistors, and then could lead to a stuck at '1'.
What about the diode from ground?  The IO transistors have both a diode to Vcco, and a diode from ground as part of their intrinsic structure.
- Can I have access to the internal user i/o pin electrical scheme?
What are you asking for?  If you want to see the schematics, the answer is no, we do not shre that with anyone.  Have you checked the signal integritry of the IO?  Overshoot?  Undershoot?  There are absolute maximum values which need to be observed for both overshoot, and undershoot.
- Can grounding problems damage user io pins?
Absolutely.  Any voltage, or current which exceeds the absoulte maximum values in the datasheet may lead to damage.  As you have 6 of them, all the same, I would look at the abs max limits, and your signal integrity (although it is unlikely to cause a failure so quickly, but a missing ground that allows a cable's stored charge to discharge into the IO could easily blow out the IO).
- Has anyone reported similar problems?
ESD damage is the most common complaint we see here in the forums.  Generally, the IO are tough, and causing them to fail takes a lot of work (or a common fault like the ground of a cable is last to connect, instead of first to connect).