Automatically run FPGA

Question

I want to make my cRIO-9012 application (RT & FPGA vi's) startup automatically on power up, i.e. make my RIO completely stand alone.
WHAT I have done so far (using LabVIEW 8.5):
    I have downloaded the wanted FPGA bitfile by right clicking FPGA target>>RIO Device Setup...
    The bitfile was downloaded under the tab 'Download Bitfile to Flash' and I also checked 'Autoload VI on Device Power Up' under the 'Device Settings' tab anjd deployed that to the RIO as well.
    I have also checked 'Run when loaded to FPGA' under FPGA Target>>Properties>>General.
THE situation so far:
    The RT vi works as expected in stand alone mode (by making the appropriate Build Specifications) as soon as I power my RIO up but the FPGA vi does not, even though I have done the above.  I know that both my RT and FPGA vi's work because I get the expected outputs when running on a host computer and connected through TCP.
I have spent a solid week reading all available documentation that I could find (discovered that FPGA Module User Manual does not seem to apply through LabVIEW 8.5) and am still no further to solving the problem
THE Question:
Can anyone tell me what I have missed OR have done incorrectly OR otherwise?  Please help.
Regards

Answer 1

Hello Van_L
I actually physically unplug and repower the RIO and just not reset it.
As for the value Property Nodes, those do exist in the RT vi.  The FPGA vi is used for I/O and the RT vi is primarily used to pull the values from the FPGA I/O (using the Property Nodes) so as to format and collate the separate I/O sources into one 122 byte string which is sent out through the RS232 VISA connection on the RT side.  The values to the front panel of the RT and FPGA vi's are only incidental for checking purposes.
I have read "you
cannot change or read the properties of front panel objects with property nodes because there
is no front panel for VIs that run on the RT target" but as I have said the front panels are only incidental, i.e. I don't know if this is actually effecting my application and if so, what I can do about it.
I've added the RTC and FPGA vi's for your perusal in a zip file and look forward to your further comments
Regards
Look forward to your further comments.
Attachments:
RTC.zip ‏273 KB