AXI Ethernet Subsystem - PHY out of reset

Question

Hi all,
I have been trying to use the AXI Ethernet Subsystem in the Mini ITX board (xc7z100ffg900-2) but I fail to take the internal PHY out of reset.
The Ethernet Subsystem is connected to a FIFO which is responsible for the block reset. I'm running the FIFO Interrupt Example that comes with the IP driver. The code gets stuck when checking for the MgtRdy bit. This seems to be because the on-chip PHY is not out of reset, since the PhyRstCmplt bit is also low.
The MGT_CLK interface is connected to the board VCO which is set up to generate a 125 MHz differential clock. The block is also connected to the board SFP.
In previous designs when I did not have a PHY (loopback setup using the MII/GMII interface) the core would work fine. This problem only came up when I instantiate the on-chip PHY. I tried using Vivado 2014.2 (1000BASE-X PCS/PMA) and Vivado 2015.1 (1G/2.5G Ethernet PCS/PMA) and no success in both cases.
Have anyone had a similar issue?
Is there any way to check if the VCO output is correct?
Thanks
 

Answer 1

Update: Phy is out of reset now but MgtRdy is still low. ISR reads 0x140.
What could be the reasons MgtRdy does not go high?