Bug with ILA CORE

hi,
i work with a xc7a75tfgg676-2c and now i had i ila core for debug, i have always this message when i open synthesized design or implemented design
[Netlist 29-73] Incorrect value '62.000000' specified for property 'CLKFBOUT_MULT_F'. The system will either use the default value or the property value will be dropped. Verify your source files. ["c:/Users/VIMS/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6288-VIMS-PC/dcp/FPGA.edf":138471]
[Netlist 29-73] Incorrect value '0.000000' specified for property 'CLKFBOUT_PHASE'. The system will either use the default value or the property value will be dropped. Verify your source files. ["c:/Users/VIMS/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6288-VIMS-PC/dcp/FPGA.edf":138472]
[Netlist 29-73] Incorrect value '50.000000' specified for property 'CLKIN1_PERIOD'. The system will either use the default value or the property value will be dropped. Verify your source files. ["c:/Users/VIMS/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6288-VIMS-PC/dcp/FPGA.edf":138473][Netlist 29-73] Incorrect value '10.000000' specified for property 'CLKIN2_PERIOD'. The system will either use the default value or the property value will be dropped. Verify your source files. ["c:/Users/VIMS/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6288-VIMS-PC/dcp/FPGA.edf":138474]
i have syntesized my design a lot of time and generated bistream too without error message or timing closure before integrated the ILA CORE.
Now if i delete the ILA CORE code, i have always the error message.
I'm no understand.

Hi,
Which version of Vivado are you using?
If you are using older version of Vivado then try using Vivado 2015.1.
I saw similar issue in 2014.4 and its fixed in 2015.1.
Also you can try using the below parameter in older version of vivado. Run this from Vivado tcl console.
set_param logicopt.enableMandatoryLopt NO
Thanks,
Deepika.

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I guess I have solved the problem, if it is a problem.
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